ATMEGA162V-8PU Atmel, ATMEGA162V-8PU Datasheet - Page 213

• Manufacturer Part Number: ATMEGA162V-8PU
• Description: IC AVR MCU 16K 8MHZ 1.8V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162V-8PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: JTAG/SPI/USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ATmega162
Boundary-scan
Order
2513K–AVR–07/09
Table 86. Boundary-scan Signals for the Analog Comparator
Table 87
selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The
scan order follows the pinout order as far as possible. Therefore, the bits of Port A and Port E is
scanned in the opposite bit order of the other ports. Exceptions from the rules are the Scan
chains for the analog circuits, which constitute the most significant bits of the scan chain regard-
less of which physical pin they are connected to. In
PXn. Control corresponds to FF1, and PXn. Pullup_enable corresponds to FF2. Bit 4, 5, 6, and
7of Port C is not in the scan chain, since these pins constitute the TAP pins when the JTAG is
enabled.
Table 87. ATmega162 Boundary-scan Order
Signal
Name
AC_IDLE
ACO
ACBG
Bit Number
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
shows the Scan order between TDI and TDO when the Boundary-scan chain is
Direction as
seen from the
Comparator
input
output
input
Description
Turns off Analog
comparator
when true
Analog
Comparator
Output
Bandgap
Reference
enable
Signal Name
AC_IDLE
ACO
ACBG
PB0.Data
PB0.Control
PB0.Pullup_Enable
PB1.Data
PB1.Control
PB1.Pullup_Enable
PB2.Data
PB2.Control
PB2.Pullup_Enable
PB3.Data
PB3.Control
PB3.Pullup_Enable
PB4.Data
PB4.Control
PB4.Pullup_Enable
Recommended
Input when Not
in Use
1
Will become
input to µC code
being executed
0
Figure
Module
Comparator
Port B
87, PXn. Data corresponds to FF0,
Output Values when
Recommended
Inputs are Used
Depends upon µC
code being executed
0
Depends upon µC
code being executed
ATmega162/V
213