ATMEGA162V-8PU Atmel, ATMEGA162V-8PU Datasheet - Page 19
ATMEGA162V-8PU
Manufacturer Part Number
ATMEGA162V-8PU
Description
IC AVR MCU 16K 8MHZ 1.8V 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA162V-8PU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
JTAG/SPI/USART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
35
Number Of Timers
4
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
Package
40PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
8 MHz
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA162V-8PU
Manufacturer:
IDT
Quantity:
74
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Data Memory Access
Times
EEPROM Data
Memory
2513K–AVR–07/09
Figure 9. Data Memory Map
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 10. On-chip Data SRAM Access Cycles
The ATmega162 contains 512 bytes of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described
in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and
the EEPROM Control Register.
Address
Memory configuration A
clk
160 Ext I/O Reg.
64 I/O Registers
Data
Data
Data Memory
External SRAM
Internal SRAM
WR
CPU
32 Registers
RD
(0 - 64K x 8)
(1024 x 8)
Compute Address
0x04FF
0x0500
0x0000 - 0x001F
0x0020 - 0x005F
0x0060 - 0x00FF
0xFFFF
0x0100
T1
Memory Access Instruction
Address valid
CPU
Memory configuration B
T2
64 I/O Registers
Data Memory
External SRAM
Internal SRAM
32 Registers
(0 - 64K x 8)
cycles as described in
(1024 x 8)
Next Instruction
0x0000 - 0x001F
0x0020 - 0x005F
0x0060
0x045F
0x0460
0xFFFF
T3
ATmega162/V
Figure
10.
19
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