ATMEGA162V-8PU Atmel, ATMEGA162V-8PU Datasheet - Page 84

• Manufacturer Part Number: ATMEGA162V-8PU
• Description: IC AVR MCU 16K 8MHZ 1.8V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162V-8PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: JTAG/SPI/USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

External
Interrupts
MCU Control Register
– MCUCR
84
ATmega162/V
The External Interrupts are triggered by the INT0, INT1, INT2 pin, or any of the PCINT15..0 pins.
Observe that, if enabled, the interrupts will trigger even if the INT2..0 or PCINT15..0 pins are
configured as outputs. This feature provides a way of generating a software interrupt. The Exter-
nal Interrupts can be triggered by a falling or rising edge or a low level (INT2 is only an edge
triggered interrupt). This is set up as indicated in the specification for the MCU Control Register
– MCUCR and Extended MCU Control Register – EMCUCR. When the external interrupt is
enabled and is configured as level triggered (only INT0/INT1), the interrupt will trigger as long as
the pin is held low. The pin change interrupt PCI1 will trigger if any enabled PCINT15..8 pin tog-
gles. Pin change interrupts PCI0 will trigger if any enabled PCINT7..0 pin toggles. The PCMSK1
and PCMSK0 Registers control which pins contribute to the pin change interrupts. Note that rec-
ognition of falling or rising edge interrupts on INT0 and INT1 requires the presence of an I/O
clock, described in
INT0/INT1, the edge interrupt on INT2, and Pin change interrupts on PCINT15..0 are detected
asynchronously. This implies that these interrupts can be used for waking the part also from
sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. This makes the MCU less sensitive to
noise. The changed level is sampled twice by the Watchdog Oscillator clock. The period of the
Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the Watchdog Oscilla-
tor is voltage dependent as shown in
wake up if the input has the required level during this sampling or if it is held until the end of the
start-up time. The start-up time is defined by the SUT Fuses as described in
Clock Options” on page
disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be
generated. The required level must be held long enough for the MCU to complete the wake up to
trigger the level interrupt.
The MCU Control Register contains control bits for interrupt sense control and general MCU
functions.
• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-bit and the corre-
sponding interrupt mask in the GICR are set. The level and edges on the external INT1 pin that
activate the interrupt are defined in
detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock
period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If
low level interrupt is selected, the low level must be held until the completion of the currently
executing instruction to generate an interrupt.
Bit
Read/Write
Initial Value
SRE
R/W
7
0
“Clock Systems and their Distribution” on page
SRW10
R/W
6
0
35. If the level is sampled twice by the Watchdog Oscillator clock but
R/W
SE
5
0
Table
“Electrical Characteristics” on page
SM1
R/W
4
0
43. The value on the INT1 pin is sampled before
ISC11
R/W
3
0
ISC10
R/W
2
0
ISC01
R/W
1
0
35. Low level interrupts on
ISC00
R/W
0
0
264. The MCU will
“System Clock and
MCUCR
2513K–AVR–07/09