ATMEGA325V-8AU Atmel, ATMEGA325V-8AU Datasheet - Page 22

• Manufacturer Part Number: ATMEGA325V-8AU
• Description: IC AVR MCU 32K 8MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA325V-8AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5
7.5.1
7.5.2
7.5.3
2570M–AVR–04/11
Register Description
EEARH and EEARL – The EEPROM Address Register
EEDR – The EEPROM Data Register
EECR – The EEPROM Control Register
• Bits 15:11 – Reserved Bits
These bits are reserved bits in the Atmel ATmega325/3250/645/6450 and will always read as
zero.
• Bits 10:0 – EEAR10:0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
1/2K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
1023/2047. The initial value of EEAR is undefined. A proper value must be written before the
EEPROM may be accessed.
Note:
• Bits 7:0 – EEDR7..0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
• Bits 7:4 – Reserved Bits
These bits are reserved bits in the Atmel ATmega325/3250/645/6450 and will always read as
zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-
rupt when EEWE is cleared.
Bit
0x22 (0x42)
0x21 (0x41)
Read/Write
Initial Value
Bit
0x20 (0x40)
Read/Write
Initial Value
Bit
0x1F (0x3F)
Read/Write
Initial Value
EEAR10 is only valid for ATmega645 and ATmega6450.
EEAR7
MSB
R/W
R/W
15
R
X
–
7
0
7
0
R
7
–
0
EEAR6
R/W
R/W
14
R
–
6
0
X
6
0
R
6
–
0
EEAR5
R/W
R/W
13
R
X
–
5
0
5
0
R
5
–
0
EEAR4
R/W
R/W
12
R
X
–
4
0
4
0
R
4
–
0
ATmega325/3250/645/6450
EEAR3
EERIE
R/W
R/W
R/W
11
R
–
3
0
X
3
0
3
0
EEAR10
EEMWE
EEAR2
R/W
R/W
R/W
R/W
10
X
X
2
2
0
2
0
EEAR9
EEAR1
EEWE
R/W
R/W
R/W
R/W
X
X
X
9
1
1
0
1
EEAR8
EEAR0
EERE
R/W
R/W
LSB
R/W
R/W
X
X
8
0
0
0
0
0
EEARH
EEARL
EEDR
EECR
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