AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 266
AT32UC3A364-ALUT
Manufacturer Part Number
AT32UC3A364-ALUT
Description
IC MCU 64KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A364-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
110
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
IrDA/SCI/SCIF/UDI
Maximum Clock Frequency
66 MHz
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
110
Ram Memory Size
64KB
Cpu Speed
66MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 266 of 1014
- Download datasheet (16Mb)
Using ECC-H code, one bit correction per sector of 512 bytes (MD.TYPECORREC=0b010)
• NPARITYn: Parity N
• WORDADDRn: corrupted Word Address in the packet number n of 512 bytes in the page
• BITADDRn: corrupted Bit Address in the packet number n of 512 bytes in the page
32072C–AVR32–2010/03
31
23
15
7
-
Once the entire main area of a page is written with data, this register content must be stored to any free location of the spare
area.
Only PR2 to PR7 registers are available in this case.
Parity calculated by the ECC-H.
During a page read, this field contains the word address (8-bit word) where an error occurred, if a single error was detected. If
multiple errors were detected, this field is meaningless.
During a page read, this field contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple
errors were detected, this field is meaningless.
30
22
14
6
-
NPARITYn[3:0]
WORDADDn[4:0]
29
21
13
5
-
28
20
12
4
-
NPARITYn[11:4]
27
19
11
3
-
26
18
10
2
-
WORDADDn[8:5]
BITADDRn
AT32UC3A3/A4
25
17
9
1
-
24
16
8
0
-
266
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