AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 669
AT32UC3A364-ALUT
Manufacturer Part Number
AT32UC3A364-ALUT
Description
IC MCU 64KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A364-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
110
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
IrDA/SCI/SCIF/UDI
Maximum Clock Frequency
66 MHz
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
110
Ram Memory Size
64KB
Cpu Speed
66MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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32072C–AVR32–2010/03
The UDDMAnSTATUS.CHEN bit is 0 and the UDDMAnSTATUS.LDNXTCHDESCEN is set indi-
cating that the DMA channel is pending until the endpoint is ready (received OUT packet).
As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit
is set to one. Then after a few cycle latency, the new descriptor is loaded from the memory and
the UDDMAnSTATUS.DESCLDSTA is set.
At the end of this DMA (for instance when the channel byte length has reached 0), the
UDDMAnCONTROL.CHEN bit is cleared, and then the UDDMAnSTATUS.CHEN bit is also
cleared. If the UDDMAnCONTROL.LDNXTCH value is one, a new descriptor is loaded.
This sequence is repeated until a last linked descriptor is processed. The last descriptor is
detected according to row 2 as shown in
At the end of the last descriptor, the UDDMAnCONTROL.CHEN bit is cleared. As a conse-
quence, after a few cycles latency, the UDDMAnSTATUS.CHEN bit is also cleared.
• Set up the chain of linked list of descripor in memory. Each descriptor is composed of 3 items
• Program the UDDMAnNEXTDESC register.
• Program the UDDMAnCONTROL according to Row 3 as shown in
: channel next descriptor address, channel destination address and channel control. The last
descriptor should be programmed according to row 2 as shown in
Figure 26-7 on page
720.
AT32UC3A3/A4
Figure 26-7 on page
Figure 26-7 on page
720.
720.
669
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