AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 92
AT32UC3A364-ALUT
Manufacturer Part Number
AT32UC3A364-ALUT
Description
IC MCU 64KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A364-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
110
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
IrDA/SCI/SCIF/UDI
Maximum Clock Frequency
66 MHz
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
110
Ram Memory Size
64KB
Cpu Speed
66MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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9.5
9.6
Table 9-1.
32072C–AVR32–2010/03
Offset
0x00
0x04
Functional Description
User Interface
WDT Register Memory Map
The WDT is enabled by writing a one to the Enable bit in the Control register (CTRL.EN). This
also enables the system RC clock (CLK_RCSYS) for the prescaler. The Prescale Select field
(PSEL) in the CTRL register selects the watchdog time-out period:
The next time-out period will begin as soon as the watchdog reset has occurred and count down
during the reset sequence. Care must be taken when selecting the PSEL field value so that the
time-out period is greater than the startup time of the chip, otherwise a watchdog reset can reset
the chip before any code has been run.
To avoid accidental disabling of the watchdog, the CTRL register must be written twice, first with
the KEY field set to 0x55, then 0xAA without changing the other bits. Failure to do so will cause
the write operation to be ignored, and the CTRL register value will not change.
The Clear register (CLR) must be written with any value with regular intervals shorter than the
watchdog time-out period. Otherwise, the device will receive a soft reset, and the code will start
executing from the boot vector.
When the WDT is enabled, it is not possible to enter Static mode. Attempting to do so will result
in entering Shutdown mode, leaving the WDT operational.
T
Control Register
WDT
Clear Register
Register
= 2
(PSEL+1)
/ f
RC
Register Name
CTRL
CLR
Read/Write
Write-only
Access
AT32UC3A3/A4
0x00000000
0x00000000
Reset
92
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