AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 895
AT32UC3A364-ALUT
Manufacturer Part Number
AT32UC3A364-ALUT
Description
IC MCU 64KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A364-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
110
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
IrDA/SCI/SCIF/UDI
Maximum Clock Frequency
66 MHz
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
110
Ram Memory Size
64KB
Cpu Speed
66MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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32.4.2
32.4.2.1
32.4.2.2
32072C–AVR32–2010/03
Start Modes
Manual mode
Automatic mode
These sizes are selected by writing the Cipher Feedback Data Size field in the MR register
(MR.CFDS).
The Start Mode field in the MR register (MR.SMOD) allows selection of the encryption (or
decryption) start mode.
The sequence is as follows:
Note:
Table 32-1.
Note:
Note:
The automatic mode is similar to the manual one, except that in this mode, as soon as the cor-
rect number of IDATAnR Registers is written, processing is automatically started without any
action in the CR register.
• Write the 128-bit/192-bit/256-bit key in the KEYWnR registers.
• Write the initialization vector (or counter) in the IVnR registers.
• Write the Data Ready bit in the Interrupt Enable Register (IER.DATRDY), depending on
• Write the data to be encrypted/decrypted in the authorized Input Data Registers (IDATAnR).
• Write the START bit in the Control Register (CR.START) to begin the encryption or the
• When the processing completes, the DATRDY bit in the Interrupt Status Register
• If an interrupt has been enabled by writing the IER.DATRDY bit, the interrupt line of the AES
• When the software reads one of the Output Data Registers (ODATAxR), the ISR.DATRDY bit
whether an interrupt is required or not at the end of processing.
decryption process.
(ISR.DATRDY) is set.
is activated.
is cleared.
Operation Mode
128-bit CFB
64-bit CFB
32-bit CFB
16-bit CFB
8-bit CFB
The Initialization Vector Registers concern all modes except ECB.
In 64-bit CFB mode, writing to IDATA3R and IDATA4R registers is not allowed and may lead to
errors in processing.
In 32-bit, 16-bit and 8-bit CFB modes, writing to IDATA2R, IDATA3R and IDATA4R registers is not
allowed and may lead to errors in processing.
ECB
CBC
OFB
CTR
Authorized Input Data Registers
IDATA1R and IDATA2R
IDATAnR to Write
IDATA1R
IDATA1R
IDATA1R
All
All
All
All
All
AT32UC3A3/A4
895
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