AT32UC3A3128-ALUT Atmel, AT32UC3A3128-ALUT Datasheet - Page 314
![IC MCU 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A3128-ALUT
Manufacturer Part Number
AT32UC3A3128-ALUT
Description
IC MCU 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A3128-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
110
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
IrDA/SCI/SCIF/UDI
Maximum Clock Frequency
66 MHz
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3128-ALUT
Manufacturer:
Atmel
Quantity:
135
- Current page: 314 of 1014
- Download datasheet (16Mb)
19.3
19.4
19.4.1
19.4.2
19.4.3
19.4.4
19.4.5
32072C–AVR32–2010/03
Block Diagram
Product Dependencies
I/O Lines
Power Management
Clocks
Interrupts
Peripherals
Figure 19-1. DMA Controller (DMACA) Block Diagram
In order to use this module, other parts of the system must be configured correctly, as described
below.
The pins used for interfacing the compliant external devices may be multiplexed with GPIO lines.
The user must first program the GPIO controller to assign the DMACA pins to their peripheral
functions.
To prevent bus errors the DMACA operation must be terminated before entering sleep mode.
The CLK_DMACA to the DMACA is generated by the Power Manager (PM). Before using the
DMACA, the user must ensure that the DMACA clock is enabled in the power manager.
The DMACA interface has an interrupt line connected to the Interrupt Controller. Handling the
DMACA interrupt requires programming the interrupt controller before configuring the DMACA.
Both the source peripheral and the destination peripheral must be set up correctly prior to the
DMA transfer.
HSB Master
HSB Slave
HSB Master
HSB Slave
I/F
I/F
DMA Controller
CFG
SRC
FSM
Channel 0
FIFO
Channel 1
FSM
DST
AT32UC3A3/A4
Generator
Interrupt
irq_dma
314
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