AT32UC3A3128-ALUT Atmel, AT32UC3A3128-ALUT Datasheet - Page 843
![IC MCU 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A3128-ALUT
Manufacturer Part Number
AT32UC3A3128-ALUT
Description
IC MCU 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A3128-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
110
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
IrDA/SCI/SCIF/UDI
Maximum Clock Frequency
66 MHz
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3128-ALUT
Manufacturer:
Atmel
Quantity:
135
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30.6.7.2
30.6.8
30.6.8.1
30.6.8.2
Figure 30-13. SR.XFRDONE During a Read Access
32072C–AVR32–2010/03
MCI Transfer Done Timings
Boot Procedure, dma mode
Definition
Read Access
XFRDONE flag
CMDRDY flag
Not busy flag
CMD line
Data
The SR.XFRDONE bit indicates exactly when the read or write sequence is finished.
During a read access, the SR.XFRDONE bit behaves as shown in
6. When Data transfer is completed, host processor shall terminate the boot stream by
1. Configure MCI2 data bus width programming SDCBUS Field in the MCI_SDCR regis-
2. Set the bytecount to 512 bytes and the blockcount to the desired number of block, writ-
3. Enable DMA transfer in the MCI_DMA register.
4. Configure DMA controller, program the total amount of data to be transferred and
5. Issue the Boot Operation Request command by writing to the MCI_CMDR register with
6. DMA controller copies the boot partition to the memory.
7. When DMA transfer is completed, host processor shall terminate the boot stream by
MCI read CMD
writing the MCI_CMDR register with SPCMD field set to BOOTEND.
ter. The BOOT_BUS_WIDTH field in the device Extended CSD register must be set
accordingly.
ing BLKLEN and BCNT fields of the MCI_BLKR Register.
enable the relevant channel.
SPCND set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data transfer”.
writing the MCI_CMDR register with SPCMD field set to BOOTEND.
Card response
1st Block
The CMDRDY flag is released 8 t
Last Block
bit
lafter the end of the card response.
AT32UC3A3/A4
Figure 30-13 on page
843.
843
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