AT32UC3A3128-ALUT Atmel, AT32UC3A3128-ALUT Datasheet - Page 728
![IC MCU 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A3128-ALUT
Manufacturer Part Number
AT32UC3A3128-ALUT
Description
IC MCU 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A3128-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
110
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
IrDA/SCI/SCIF/UDI
Maximum Clock Frequency
66 MHz
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3128-ALUT
Manufacturer:
Atmel
Quantity:
135
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26.8.3.5
Register Name:
Access Type:
Offset:
Reset Value:
• DMAnINTE: DMA Channel n Interrupt Enable
• PnINTE: Pipe n Interrupt Enable
• HWUPIE: Host Wake-Up Interrupt Enable
• HSOFIE: Host Start of Frame Interrupt Enable
• RXRSMIE: Upstream Resume Received Interrupt Enable
• RSMEDIE: Downstream Resume Sent Interrupt Enable
• RSTIE: USB Reset Sent Interrupt Enable
• DDISCIE: Device Disconnection Interrupt Enable
• DCONNIE: Device Connection Interrupt Enable
32072C–AVR32–2010/03
DMA7INTE
P7INTE
31
23
15
7
-
-
This bit is set when the DMAnINTES bit is written to one. This will enable the DMA Channel n Interrupt (DMAnINT).
This bit is cleared when the DMAnINTEC bit is written to one. This will disable the DMA Channel n Interrupt (DMAnINT).
This bit is set when the PnINTES bit is written to one. This will enable the Pipe n Interrupt (PnINT).
This bit is cleared when the PnINTEC bit is written to one. This will disable the Pipe n Interrupt (PnINT).
This bit is set when the HWUPIES bit is written to one. This will enable the Host Wake-up Interrupt (HWUPI).
This bit is cleared when the HWUPIEC bit is written to one. This will disable the Host Wake-up Interrupt (HWUPI).
This bit is set when the HSOFIES bit is written to one. This will enable the Host Start of Frame interrupt (HSOFI).
This bit is cleared when the HSOFIEC bit is written to one. This will disable the Host Start of Frame interrupt (HSOFI).
This bit is set when the RXRSMIES bit is written to one. This will enable the Upstream Resume Received interrupt (RXRSMI).
This bit is cleared when the RXRSMIEC bit is written to one. This will disable the Downstream Resume interrupt (RXRSMI).
This bit is set when the RSMEDIES bit is written to one. This will enable the Downstream Resume interrupt (RSMEDI).
This bit is cleared when the RSMEDIEC bit is written to one. This will disable the Downstream Resume interrupt (RSMEDI).
This bit is set when the RSTIES bit is written to one. This will enable the USB Reset Sent interrupt (RSTI).
This bit is cleared when the RSTIEC bit is written to one. This will disable the USB Reset Sent interrupt (RSTI).
This bit is set when the DDISCIES bit is written to one. This will enable the Device Disconnection interrupt (DDISCI).
This bit is cleared when the DDISCIEC bit is written to one. This will disable the Device Disconnection interrupt (DDISCI).
This bit is set when the DCONNIES bit is written to one. This will enable the Device Connection interrupt (DCONNI).
This bit is cleared when the DCONNIEC bit is written to one. This will disable the Device Connection interrupt (DCONNI).
Host Global Interrupt Enable Register
DMA6INTE
HWUPIE
P6INTE
30
22
14
6
-
UHINTE
Read-Only
0x0410
0x00000000
DMA5INTE
HSOFIE
P5INTE
29
21
13
5
-
DMA4INTE
RXRSMIE
P4INTE
28
20
12
4
-
DMA3INTE
RSMEDIE
P3INTE
27
19
11
3
-
DMA2INTE
P2INTE
RSTIE
26
18
10
2
-
DMA1INTE
AT32UC3A3/A4
DDISCIE
P1INTE
25
17
9
1
-
DCONNIE
P0INTE
24
16
8
0
-
-
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