AT32UC3A3128-ALUT Atmel, AT32UC3A3128-ALUT Datasheet - Page 357
![IC MCU 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A3128-ALUT
Manufacturer Part Number
AT32UC3A3128-ALUT
Description
IC MCU 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A3128-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
110
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
IrDA/SCI/SCIF/UDI
Maximum Clock Frequency
66 MHz
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3128-ALUT
Manufacturer:
Atmel
Quantity:
135
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19.12.7
Name:
Access Type:
Offset:
Reset Value:
• DEST_PER: Destination Hardware Handshaking Interface
Assigns a hardware handshaking interface (0 - DMAH_NUM_HS_INT-1) to the destination of channel x if the
CFGx.HS_SEL_DST field is 0. Otherwise, this field is ignored. The channel can then communicate with the destination
peripheral connected to that interface via the assigned hardware handshaking interface.
For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking
interface.
• SRC_PER: Source Hardware Handshaking Interface
Assigns a hardware handshaking interface (0 - DMAH_NUM_HS_INT-1) to the source of channel x if the
CFGx.HS_SEL_SRC field is 0. Otherwise, this field is ignored. The channel can then communicate with the source periph-
eral connected to that interface via the assigned hardware handshaking interface.
For correct DMACA operation, only one peripheral (source or destination) should be assigned to the same handshaking
interface.
• PROTCTL: Protection Control
Bits used to drive the System Bus HPROT[3:1] bus. The System Bus Specification recommends that the default value of
HPROT indicates a non-cached, nonbuffered, privileged data access. The reset value is used to indicate such an access.
HPROT[0] is tied high as all transfers are data accesses as there are no opcode fetches. There is a one-to-one mapping of
these register bits to the HPROT[3:1] master interface signals.
• FIFO_MODE: R/W 0x0 FIFO Mode Select
Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced.
32072C–AVR32–2010/03
SRC_PER[0]
31
23
15
7
-
-
-
0 = Space/data available for single System Bus transfer of the specified transfer width.
1 = Space/data available is greater than or equal to half the FIFO depth for destination transfers and less than half the FIFO
depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer.
Configuration Register for Channel x High
30
22
14
6
-
-
-
CFGxH
Read/Write
0x044 + [x * 0x58]
0x00000004
29
21
13
5
-
-
-
DEST_PER
28
20
12
4
-
-
PROTCTL
27
19
11
3
-
-
26
18
10
2
-
-
SRC_PER[3:1]
FIFO_MODE
AT32UC3A3/A4
25
17
9
1
-
-
FCMODE
24
16
8
0
-
-
357
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