AT32UC3A3128-ALUT Atmel, AT32UC3A3128-ALUT Datasheet - Page 445
![IC MCU 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A3128-ALUT
Manufacturer Part Number
AT32UC3A3128-ALUT
Description
IC MCU 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A3128-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
110
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
IrDA/SCI/SCIF/UDI
Maximum Clock Frequency
66 MHz
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3128-ALUT
Manufacturer:
Atmel
Quantity:
135
- Current page: 445 of 1014
- Download datasheet (16Mb)
22.8.2.2
22.8.2.3
32072C–AVR32–2010/03
Setting Up and Performing a Transfer
Address Matching
Figure 22-6. Bus Timing Diagram
Operation of TWIS is mainly controlled by the Control Register (CR). The following list presents
the main steps in a typical communication:
The interrupt system can be set up to give interrupt request on specific events or error condi-
tions, for example when a byte has been received.
The NBYTES register is only used in SMBus mode, when PEC is enabled. In I²C mode or in
SMBus mode when PEC is disabled, the NBYTES register is not used, and should be written to
0. NBYTES is updated by hardware, so in order to avoid hazards, software updates of NBYTES
can only be done through writes to the NBYTES register.
TWIS can be set up to match several different addresses. More than one address match may be
enabled simultaneously, allowing TWIS to be assigned to several addresses. The address
matching phase is initiated after a START or REPEATED START condition. When TWIS
receives an address that generates an address match, an ACK is automatically returned to the
master.
In I²C mode:
In SMBus mode:
1. Before any transfers can be performed, bus timings must be configured by program-
2. If a DMA controller is to be used for the transfers, it must be set up.
3. The Control Register (CR) must be configured with information such as the slave
• The address in CR.ADR is checked for address match if CR.SMATCH is set.
• The General Call address is checked for address match if CR.GCMATCH is set.
ming the Timing Register (TR).
address, SMBus mode, Packet Error Checking (PEC), number of bytes to transfer, and
which addresses to match.
S
t
t LOW
HD:STA
t
SU:DAT
t HIGH
t
HD:DAT
t LOW
t
t
SU:DAT
SU:STA
Sr
AT32UC3A3/A4
t
SU:STO
P
445
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