ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 136

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.13.1
13.13.1.1
13.13.1.2
13.13.1.3
13.13.1.4
13.13.1.5
136
MUL
MLA
MULS
MULLT
MLS
SAM3U Series
MUL, MLA, and MLS
Syntax
Operation
Restrictions
Condition flags
Examples
R10, R2, R5
R10, R2, R1, R5 ; Multiply with accumulate, R10 = (R2 x R1) + R5
R0, R2, R2
R2, R3, R2
R4, R5, R6, R7
Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and pro-
ducing a 32-bit result.
where:
cond
S
result of the operation, see
Rd
Rn, Rm
Ra
The MUL instruction multiplies the values from Rn and Rm, and places the least significant 32
bits of the result in Rd.
The MLA instruction multiplies the values from Rn and Rm, adds the value from Ra, and places
the least significant 32 bits of the result in Rd.
The MLS instruction multiplies the values from Rn and Rm, subtracts the product from the value
from Ra, and places the least significant 32 bits of the result in Rd.
The results of these instructions do not depend on whether the operands are signed or
unsigned.
In these instructions, do not use SP and do not use PC.
If you use the S suffix with the MUL instruction:
If S is specified, the MUL instruction:
• Rd, Rn, and Rm must all be in the range R0 to R7
• Rd must be the same as Rm
• you must not use the cond suffix.
• updates the N and Z flags according to the result
• does not affect the C and V flags.
MUL{S}{cond} {Rd,} Rn, Rm ; Multiply
MLA{cond} Rd, Rn, Rm, Ra
MLS{cond} Rd, Rn, Rm, Ra
; Multiply, R10 = R2 x R5
; Multiply with flag update, R0 = R2 x R2
; Conditionally multiply, R2 = R3 x R2
; Multiply with subtract, R4 = R7 - (R5 x R6)
is an optional condition code, see
is an optional suffix. If S is specified, the condition code flags are updated on the
is the destination register. If Rd is omitted, the destination register is Rn.
are registers holding the values to be multiplied.
is a register holding the value to be added or subtracted from.
“Conditional execution” on page
; Multiply with accumulate
; Multiply with subtract
“Conditional execution” on page
100.
6430D–ATARM–25-Mar-11
100.