ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 885

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 38-14. Comparison Waveform
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Comparison Update
Comparison Match
CVMVUPD
CUPRUPD
CUPRCNT
CTRUPD
CPRUPD
CPRCNT
CVUPD
CCNT0
CMPM
CMPU
CUPR
CVM
CPR
CTR
CV
0x6
0x1
0x1
0x3
0x6
0x1
0x1
0x3
0x0
0x0
The update of the comparison x configuration and the comparison x value is triggered periodi-
cally after the comparison x update period. It is defined by the field CUPR in the PWM_CMPMx.
The comparison unit has an update period counter independent from the period counter to trig-
ger this update. When the value of the comparison update period counter CUPRCNT (in
PWM_CMPMx) reaches the value defined by CUPR, the update is triggered. The comparison x
update period CUPR itself can be updated while the channel 0 is enabled by using the
PWM_CMPMUPDx register.
CAUTION: to be taken into account, the write of the register PWM_CMPVUPDx must be fol-
lowed by a write of the register PWM_CMPMUPDx.
The comparison match and the comparison update can be source of an interrupt, but only if it is
enabled and not masked. These interrupts can be enabled by the
ter 2”
and the comparison update interrupt are reset by reading the
and disabled by the
0x1
0x1
0x2
0x2
0x0
0x2
0x3
0x2
0x3
0x1
“PWM Interrupt Disable Register
0x2
0x2
0x0
0x3
0x2
0x0
0x1
0x1
0x2
0x2
0x0
0x3
0x6
0x1
0x0
2”. The comparison match interrupt
“PWM Interrupt Status Register
0x2
0x1
“PWM Interrupt Enable Regis-
SAM3U Series
SAM3U Series
0x6
0x0
0x2
0x1
0x3
885
885
2”.