ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 235

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.4.3.1
14.4.4
14.4.5
6430D–ATARM–25-Mar-11
FPB (Flash Patch Breakpoint)
DWT (Data Watchpoint and Trace)
SW-DP and JTAG-DP Selection Mechanism
When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace. The asyn-
chronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace
can only be used with SW-DP, not JTAG-DP.
Table 14-2.
SW-DP or JTAG-DP mode is selected when JTAGSEL is low. It is not possible to switch directly
between SWJ-DP and JTAG boundary scan operations. A chip reset must be performed after
JTAGSEL is changed.
Debug port selection mechanism is done by sending specific SWDIOTMS sequence. The JTAG-
DP is selected by default after reset.
The FPB:
The FPB unit contains:
The DWT contains four comparators which can be configured to generate the following:
Pin Name
TMS/SWDIO
TCK/SWCLK
TDI
TDO/TRACESWO
• Switch from JTAG-DP to SW-DP. The sequence is:
• Switch from SWD to JTAG. The sequence is:
• Implements hardware breakpoints
• Patches code and data from code space to system space.
• Two literal comparators for matching against literal loads from Code space, and remapping to
• Six instruction comparators for matching against instruction fetches from Code space and
• Alternatively, comparators can also be configured to generate a Breakpoint instruction to the
• PC sampling packets at set intervals
• PC or Data watchpoint packets
a corresponding area in System space.
remapping to a corresponding area in System space.
processor core on a match.
– Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
– Send the 16-bit sequence on SWDIOTMS = 0111100111100111 (0x79E7 MSB first)
– Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
– Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
– Send the 16-bit sequence on SWDIOTMS = 0011110011100111 (0x3CE7 MSB first)
– Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
SWJ-DP Pin List
JTAG Port
TMS
TDO
TCK
TDI
TRACESWO (optional: trace)
SAM3U Series
Serial Wire Debug Port
SWCLK
SWDIO
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