ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 999

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

39.7.17
Name:
Address:
Access:
• FRCESTALL: Stall Handshake Request
0 = no effect.
1= If set a STALL answer will be done to the host for the next handshake.
This bit is reset by hardware upon received SETUP.
• TOGGLESQ_STA: Toggle Sequencing
Toggle Sequencing:
Notes:
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
SHRT_PCKT
NAK_OUT
These bits are set by hardware to indicate the PID data of the current bank:
Value
– IN endpoint: it indicates the PID Data Toggle that will be used for the next packet sent. This is not relative to
– CONTROL and OUT endpoint:
31
23
15
0
1
2
3
7
TOGGLESQ_STA
the current bank.
1. In OUT transfer, the Toggle information is meaningful only when the current bank is busy (Received OUT Data = 1).
2. These bits are updated for OUT transfer:
3. For High Bandwidth Isochronous Out endpoint, it is recommended to check the UDPHS_EPTSTAx/ERR_TRANS bit to know
4. This field is reset to DATA1 by the UDPHS_EPTCLRSTAx register TOGGLESQ bit, and by UDPHS_EPTCTLDISx (disable
UDPHS Endpoint Status Register
-
-
if the toggle sequencing is correct or not.
endpoint).
a new data has been written into the current bank.
the user has just cleared the Received OUT Data bit to switch to the next bank.
UDPHS_EPTSTAx [x=0..6]
0x400A411C [0], 0x400A413C [1], 0x400A415C [2], 0x400A417C [3], 0x400A419C [4], 0x400A41BC [5],
0x400A41DC [6]
Read-only
Name
DATA0
DATA1
DATA2
MDATA
ERR_FLUSH
NAK_IN/
30
22
14
6
BYTE_COUNT
Description
DATA0
DATA1
Data2 (only for High Bandwidth Isochronous Endpoint)
MData (only for High Bandwidth Isochronous Endpoint)
ERR_CRISO/
ERR_NBTRA
STALL_SNT/
FRCESTALL
29
21
13
5
ERR_FL_ISO
RX_SETUP/
28
20
12
4
–
BYTE_COUNT
TX_PK_RDY/
ERR_TRANS
27
19
11
BUSY_BANK_STA
3
–
TX_COMPLT
26
18
10
2
–
RX_BK_RDY/
KILL_BANK
SAM3U Series
SAM3U Series
25
17
CURRENT_BANK/
9
1
–
CONTROL_DIR
ERR_OVFLW
24
16
8
0
–
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