ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 882

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

882
882
SAM3U Series
SAM3U Series
Sequence for Method 3:
1. Select the automatic write of duty-cycle values and automatic update by setting the field
2. Define the synchronous channels by the bits SYNCx in the PWM_SCM register.
3. Define the update period by the field UPR in the PWM_SCUP register.
4. Define when the WRDY flag and the corresponding PDC transfer request must be set in
5. Define the PDC transfer settings for the duty-cycle values and enable it in the PDC
6. Enable the synchronous channels by writing CHID0 in the PWM_ENA register.
7. If an update of the period value and/or of the dead-time values is required, write regis-
8. Set UPDULOCK to 1 in PWM_SCUC.
9. The update of these registers will occur at the beginning of the next PWM period. At
10. If an update of the update period value is required, check first that write of a new update
11. Write the register that needs to be updated (PWM_SCUPUPD).
12. The update of this register will occur at the next PWM period of the synchronous chan-
13. Check the end of the PDC transfer by the flag ENDTX. If the transfer has ended, define
UPDM to 2 in the PWM_SCM register.
the update period by the PTRM bit and the PTRCS field in the PWM_SCM register (at
the end of the update period or when a comparison matches).
registers
ters that need to be updated (PWM_CPRDUPDx, PWM_DTUPDx), else go to
this moment the bit UPDULOCK is reset, go to
value is possible by polling the flag WRDY (or by waiting for the corresponding inter-
rupt) in the PWM_ISR2 register, else go to
nels when the Update Period is elapsed. Go to
a new PDC transfer in the PDC registers for new duty-cycle values. Go to
Step 13.
Step 7.
Step 10.
for new values.
for new values.
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Step 5.
Step 10.