ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 866

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

38.6
38.6.1
866
866
Functional Description
SAM3U Series
SAM3U Series
PWM Clock Generator
Table 38-4.
Note:
The
Figure 38-2. Functional View of the Clock Generator Block Diagram
Fault Inputs
Main OSC
PA18
PA11
PA12
• Clocked by the master clock (MCK), the clock generator module provides 13 clocks.
• Each channel can independently choose one of the clock generator outputs.
• Each channel generates an output waveform with attributes that can be defined
independently for each channel through the user interface registers.
PWM
1. FPOL bit in PWMC_FMR.
macrocell is primarily composed of a clock generator module and
Fault Inputs
External PWM Fault Input Number
–
PWMFI2
PWMFI0
PWMFI1
MCK
modulo n counter
PREA
PREB
PWM_MR
PWM_MR
Divider A
Divider B
DIVA
DIVB
Polarity Level
1
User Defined
User Defined
User Defined
MCK
MCK/2
MCK/4
MCK/8
MCK/16
MCK/32
MCK/64
MCK/128
MCK/256
MCK/512
MCK/1024
clkA
clkB
(1)
4
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Fault Input ID
0
1
2
3
channels.