AT32UC3A0512-ALUT Atmel, AT32UC3A0512-ALUT Datasheet - Page 266
![IC MCU AVR32 512KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A0512-ALUT
Manufacturer Part Number
AT32UC3A0512-ALUT
Description
IC MCU AVR32 512KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A0512-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Package
144LQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
66 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
69
Interface Type
Ethernet/I2S/JTAG/SPI/TWI/USART
Number Of Timers
3
Processor Series
AT32UC3x
Core
AVR32
Data Ram Size
64 KB
Maximum Clock Frequency
66 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105, ATAVRRZ600
Minimum Operating Temperature
- 40 C
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0512-ALUT
Manufacturer:
ATMEL
Quantity:
2 155
Part Number:
AT32UC3A0512-ALUT
Manufacturer:
AT
Quantity:
20 000
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Figure 25-8. Transmitter Block Diagram
25.7.3
32058J-AVR32-04/11
Transmitter Clock
RX_FRAME_SYNC
Receiver Operations
TX_FRAME_SYNC
TFMR.DATLEN
TCMR.STTDLY
TFMR.FSDEN
Selector
Start
A received frame is triggered by a start event and can be followed by synchronization data
before data transmission.
The start event is configured setting the Receive Clock Mode Register (RCMR).
“25.7.4” on page 267.
The frame synchronization is configured setting the Receive Frame Mode Register (RFMR).
Section “25.7.5” on page 269.
The receiver uses a shift register clocked by the receiver clock signal and the start mode
selected in the RCMR. The data is transferred from the shift register depending on the data for-
mat selected.
When the receiver shift register is full, the SSC transfers this data in the holding register, the sta-
tus flag RXRDY is set in SR and the data can be read in the receiver holding register. If another
transfer occurs before read of the RHR register, the status flag OVERUN is set in SR and the
receiver shift register is transferred in the RHR register.
TFMR.MSBF
THR
Transmit Shift Register
TFMR.DATDEF
0
1
TSHR
0
1
TFMR.FSLEN
TCMR.STTDLY
TFMR.DATNB
TFMR.FSDEN
CR.TXEN
CR.TXDIS
SR.TXEN
AT32UC3A
TX_DATA
See Section
See
266
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