AT32UC3A0512-ALUT Atmel, AT32UC3A0512-ALUT Datasheet - Page 570
![IC MCU AVR32 512KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A0512-ALUT
Manufacturer Part Number
AT32UC3A0512-ALUT
Description
IC MCU AVR32 512KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A0512-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Package
144LQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
66 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
69
Interface Type
Ethernet/I2S/JTAG/SPI/TWI/USART
Number Of Timers
3
Processor Series
AT32UC3x
Core
AVR32
Data Ram Size
64 KB
Maximum Clock Frequency
66 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105, ATAVRRZ600
Minimum Operating Temperature
- 40 C
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0512-ALUT
Manufacturer:
ATMEL
Quantity:
2 155
Part Number:
AT32UC3A0512-ALUT
Manufacturer:
AT
Quantity:
20 000
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30.8.2.9
Offset:
Register Name:
Access Type:
Reset Value:
• EPENX, X in [0..6]: Endpoint X Enable
Set to enable the endpoint X.
Clear to disable the endpoint X, what forces the endpoint X state to inactive (no answer to USB requests) and resets the
endpoint X registers (UECFGX, UESTAX, UECONX) but not the endpoint configuration (ALLOC, EPBK, EPSIZE, EPDIR,
EPTYPE).
• EPRSTX, X in [0..6]: Endpoint X Reset
Set by software to reset the endpoint X FIFO prior to any other operation, upon hardware reset or when a USB bus reset
has been received. This resets the endpoint X registers (UECFGX, UESTAX, UECONX) but not the endpoint configuration
(ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE).
All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle Sequence
field (DTSEQ) which can be cleared by setting the RSTDT bit (by setting the RSTDTS bit).
The endpoint configuration remains active and the endpoint is still enabled.
Then, clear by software to complete the reset operation and to start using the FIFO.
Cleared by hardware upon receiving a USB reset.
32058J–AVR32–04/11
31
23
15
–
–
–
7
–
USB Endpoint Enable/Reset Register (UERST)
EPRST6
EPEN6
rwu
30
22
14
rw
–
0
–
6
0
EPRST5
EPEN5
rwu
29
21
13
rw
–
0
–
5
0
0x001C
UERST
Read/Write
0x00000000
EPRST4
EPEN4
rwu
28
20
12
rw
–
0
–
4
0
EPRST3
EPEN3
rwu
27
19
11
rw
–
0
–
3
0
EPRST2
EPEN2
rwu
26
18
10
rw
–
0
–
2
0
EPRST1
EPEN1
rwu
25
17
rw
–
0
9
–
1
0
AT32UC3A
EPRST0
EPEN0
rwu
24
16
rw
–
0
8
–
0
0
570
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