AT32UC3A0512-ALUT Atmel, AT32UC3A0512-ALUT Datasheet - Page 573
AT32UC3A0512-ALUT
Manufacturer Part Number
AT32UC3A0512-ALUT
Description
IC MCU AVR32 512KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A0512-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Package
144LQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
66 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
69
Interface Type
Ethernet/I2S/JTAG/SPI/TWI/USART
Number Of Timers
3
Processor Series
AT32UC3x
Core
AVR32
Data Ram Size
64 KB
Maximum Clock Frequency
66 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105, ATAVRRZ600
Minimum Operating Temperature
- 40 C
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0512-ALUT
Manufacturer:
ATMEL
Quantity:
2 155
Part Number:
AT32UC3A0512-ALUT
Manufacturer:
AT
Quantity:
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30.8.2.11
Offset:
Register Name:
Access Type:
Reset Value:
• TXINI: Transmitted IN Data Interrupt Flag
For control endpoints:
For isochronous, bulk and interrupt IN endpoints:
This bit is inactive (cleared) for isochronous, bulk and interrupt OUT endpoints.
• RXOUTI: Received OUT Data Interrupt Flag
For control endpoints:
32058J–AVR32–04/11
PACKET
SHORT
Set by hardware when the current bank is ready to accept a new IN packet. This triggers an EPXINT interrupt if
TXINE = 1.
Shall be cleared by software (by setting the TXINIC bit) to acknowledge the interrupt and to send the packet.
Set by hardware at the same time as FIFOCON when the current bank is free. This triggers an EPXINT interrupt if
TXINE = 1.
Shall be cleared by software (by setting the TXINIC bit) to acknowledge the interrupt, what has no effect on the end-
point FIFO.
The software then writes into the FIFO and clears the FIFOCON bit to allow the USB controller to send the data. If
the IN endpoint is composed of multiple banks, this also switches to the next bank. The TXINI and FIFOCON bits are
updated by hardware in accordance with the status of the next bank.
TXINI shall always be cleared before clearing FIFOCON.
Set by hardware when the current bank contains a bulk OUT packet (data or status stage). This triggers an EPXINT
interrupt if RXOUTE = 1.
31
23
15
ru
–
0
0
7
0
CURRBK
USB Endpoint X Status Register (UESTAX)
ru
STALLEDI/
CRCERRI
30
22
14
ru
0
0
0
6
0
BYCT
ru
OVERFI
29
21
13
ru
0
0
0
5
0
0x0130 + X . 0x04
UESTAX, X in [0..6]
Read-Only
0x00000100
NBUSYBK
ru
NAKINI
28
20
12
ru
0
0
0
4
0
NAKOUTI
BYCT
27
19
11
ru
ru
0
–
–
3
0
UNDERFI
RXSTPI/
CFGOK
26
18
10
ru
ru
0
0
–
2
0
CTRLDIR
RXOUTI
25
17
ru
ru
0
0
9
0
1
0
AT32UC3A
DTSEQ
ru
RWALL
TXINI
24
16
ru
ru
0
0
8
1
0
0
573
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