AT32UC3A0512-ALUT Atmel, AT32UC3A0512-ALUT Datasheet - Page 345
![IC MCU AVR32 512KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A0512-ALUT
Manufacturer Part Number
AT32UC3A0512-ALUT
Description
IC MCU AVR32 512KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A0512-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Package
144LQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
66 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
69
Interface Type
Ethernet/I2S/JTAG/SPI/TWI/USART
Number Of Timers
3
Processor Series
AT32UC3x
Core
AVR32
Data Ram Size
64 KB
Maximum Clock Frequency
66 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105, ATAVRRZ600
Minimum Operating Temperature
- 40 C
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0512-ALUT
Manufacturer:
ATMEL
Quantity:
2 155
Part Number:
AT32UC3A0512-ALUT
Manufacturer:
AT
Quantity:
20 000
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• PAR: Parity Type
• SYNC/CPHA: Synchronous Mode Select or SPI Clock Phase
SYNC = 0: USART operates in Asynchronous Mode.
SYNC = 1: USART operates in Synchronous Mode.
CPHA = 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
CPHA = 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is used
with CPOL to produce the required clock/data relationship between master and slave devices.
• CHRL: Character Length.
• USCLKS: Clock Selection
32058J–AVR32–04/11
0
1
1
0
0
0
0
1
1
– If USART does not operate in SPI Mode (MODE is … 0xE and 0xF):
– If USART operates in SPI Mode (MODE = 0xE or 0xF):
0
0
1
1
0
0
1
1
USCLKS
CHRL
PAR
1
0
1
0
0
1
1
0
1
0
1
0
1
1.5 stop bits
2 stop bits
Reserved
0
1
0
1
0
1
0
1
x
x
Character Length
5 bits
6 bits
7 bits
8 bits
Parity Type
Even parity
Odd parity
Parity forced to 0 (Space)
Parity forced to 1 (Mark)
No parity
Multidrop mode
Selected Clock
CLK_USART
CLK_USART
Reserved
CLK
/DIV (DIV = xx)
Reserved
2 stop bits
Reserved
AT32UC3A
345
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