P87LPC764BDH,512 NXP Semiconductors, P87LPC764BDH,512 Datasheet - Page 29

• Manufacturer Part Number: P87LPC764BDH,512
• Description: IC 80C51 MCU 4K OTP 20-TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC700r

Specifications of P87LPC764BDH,512

• Program Memory Type: OTP
• Program Memory Size: 4KB (4K x 8)
• Package / Case: 20-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, WDT
• Number Of I /o: 18
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: P87LPC7x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C/UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Package: 20TSSOP
• Device Core: 80C51
• Family Name: 87LP
• Maximum Speed: 20 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM10063 - PROGRAMMER LPC700 P76XLCPOM10050 - EMULATOR LPC700 PDS76X
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1259-5; 935267867512; P87LPC764BDH

Philips Semiconductors
Timer/Counters
The P87LPC764 has two general purpose counter/timers which are
upward compatible with the standard 80C51 Timer 0 and Timer 1.
Both can be configured to operate either as timers or event counters
(see Figure 22). An option to automatically toggle the T0 and/or T1
pins upon timer overflow has been added.
In the “Timer” function, the register is incremented every machine
cycle. Thus, one can think of it as counting machine cycles. Since a
machine cycle consists of 6 CPU clock periods, the count rate is 1/6
of the CPU clock frequency. Refer to the section Enhanced CPU for
a description of the CPU clock.
In the “Counter” function, the register is incremented in response to
a 1-to-0 transition at its corresponding external input pin, T0 or T1.
In this function, the external input is sampled once during every
2003 Sep 03
Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
TMOD
TMOD.6
TMOD.2
BIT
TMOD.7
TMOD.5, 4
TMOD.3
TMOD.1, 0
Address: 89h
Not Bit Addressable
SYMBOL
M1, M0
M1, M0
M1, M0
GATE
GATE
C/T
C/T
0 0
0 1
1 0
1 1
GATE
7
FUNCTION
Gating control for Timer 1. When set, Timer/Counter is enabled only while the INT1 pin is high and
the TR1 control pin is set. When cleared, Timer 1 is enabled when the TR1 control bit is set.
Timer or Counter Selector for Timer 1. Cleared for Timer operation (input from internal system clock.)
Set for Counter operation (input from T1 input pin).
Mode Select for Timer 1 (see table below).
Gating control for Timer 0. When set, Timer/Counter is enabled only while the INT0 pin is high and
the TR0 control pin is set. When cleared, Timer 0 is enabled when the TR0 control bit is set.
Timer or Counter Selector for Timer 0. Cleared for Timer operation (input from internal system clock.)
Set for Counter operation (input from T0 input pin).
Mode Select for Timer 0 (see table below).
Timer Mode
8048 Timer “TLn” serves as 5-bit prescaler.
16-bit Timer/Counter “THn” and “TLn” are cascaded; there is no prescaler.
8-bit auto-reload Timer/Counter. THn holds a value which is loaded into TLn when it overflows.
Timer 0 is a dual 8-bit Timer/Counter in this mode. TL0 is an 8-bit Timer/Counter controlled by the
standard Timer 0 control bits. TH0 is an 8-bit timer only, controlled by the Timer 1 control bits (see
text). Timer 1 in this mode is stopped.
Figure 22. Timer/Counter Mode Control Register (TMOD)
C/T
6
T1
M1
5
M0
4
28
GATE
maximum count rate is 1/6 of the CPU clock frequency. There are no
3
machine cycle. When the samples of the pin state show a high in
one cycle and a low in the next cycle, the count is incremented. The
new count value appears in the register during the cycle following
the one in which the transition was detected. Since it takes 2
machine cycles (12 CPU clocks) to recognize a 1-to-0 transition, the
restrictions on the duty cycle of the external input signal, but to
ensure that a given level is sampled at least once before it changes,
it should be held for at least one full machine cycle.
The “Timer” or “Counter” function is selected by control bits C/T in
the Special Function Register TMOD. In addition to the “Timer” or
“Counter” selection, Timer 0 and Timer 1 have four operating
modes, which are selected by bit-pairs (M1, M0) in TMOD. Modes 0,
1, and 2 are the same for both Timers/Counters. Mode 3 is different.
The four operating modes are described in the following text.
C/T
2
T0
M1
1
M0
0
P87LPC764
Reset Value: 00h
SU01171
Product data