P87LPC764BDH,512 NXP Semiconductors, P87LPC764BDH,512 Datasheet - Page 44

• Manufacturer Part Number: P87LPC764BDH,512
• Description: IC 80C51 MCU 4K OTP 20-TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC700r

Specifications of P87LPC764BDH,512

• Program Memory Type: OTP
• Program Memory Size: 4KB (4K x 8)
• Package / Case: 20-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, WDT
• Number Of I /o: 18
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: P87LPC7x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C/UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Package: 20TSSOP
• Device Core: 80C51
• Family Name: 87LP
• Maximum Speed: 20 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM10063 - PROGRAMMER LPC700 P76XLCPOM10050 - EMULATOR LPC700 PDS76X
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1259-5; 935267867512; P87LPC764BDH

Philips Semiconductors
Additional Features
The AUXR1 register contains several special purpose control bits that
relate to several chip features. AUXR1 is described in Figure 35.
Software Reset
The SRST bit in AUXR1 allows software the opportunity to reset the
processor completely, as if an external reset or watchdog reset had
occurred. If a value is written to AUXR1 that contains a 1 at bit
position 3, all SFRs will be initialized and execution will resume at
program address 0000. Care should be taken when writing to
AUXR1 to avoid accidental software resets.
Dual Data Pointers
The dual Data Pointer (DPTR) adds to the ways in which the
processor can specify the address used with certain instructions.
The DPS bit in the AUXR1 register selects one of the two Data
Pointers. The DPTR that is not currently selected is not accessible
to software unless the DPS bit is toggled.
Specific instructions affected by the Data Pointer selection are:
2003 Sep 03
INC
JMP
Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
AUXR1
DPTR
@A+DPTR
BIT
AUXR1.7
AUXR1.6
AUXR1.5
AUXR1.4
AUXR1.3
AUXR1.2
AUXR1.1
AUXR1.0
Address: A2h
Not Bit Addressable
SYMBOL
SRST
LPEP
BOD
DPS
KBF
BOI
Increments the Data Pointer by 1.
Jump indirect relative to DPTR value.
—
—
KBF
7
FUNCTION
Keyboard Interrupt Flag. Set when any pin of port 0 that is enabled for the Keyboard Interrupt
function goes low. Must be cleared by software.
Brown Out Disable. When set, turns off brownout detection and saves power. See Power
Monitoring Functions section for details.
Brown Out Interrupt. When set, prevents brownout detection from causing a chip reset and allows
the brownout detect function to be used as an interrupt. See the Power Monitoring Functions
section for details.
Low Power EPROM control bit. Allows power savings in low voltage systems. Set by software. Can
only be cleared by power-on or brownout reset. See the Power Reduction Modes section for
details.
Software Reset. When set by software, resets the 87LPC764 as if a hardware reset occurred.
This bit contains a hard-wired 0. Allows toggling of the DPS bit by incrementing AUXR1, without
interfering with other bits in the register.
Reserved for future use. Should not be set to 1 by user programs.
Data Pointer Select. Chooses one of two Data Pointers for use by the program. See text for details.
BOD
6
BOI
5
Figure 35. AUXR1 Register
LPEP
4
43
Also, any instruction that reads or manipulates the DPH and DPL
registers (the upper and lower bytes of the current DPTR) will be
affected by the setting of DPS. The MOVX instructions have limited
application for the P87LPC764 since the part does not have an
external data bus. However, they may be used to access EPROM
configuration information (see EPROM Characteristics section).
Bit 2 of AUXR1 is permanently wired as a logic 0. This is so that the
DPS bit may be toggled (thereby switching Data Pointers) simply by
incrementing the AUXR1 register, without the possibility of
inadvertently altering other bits in the register.
SRST
MOV
MOVC A, @A+DPTR
MOVX A, @DPTR
MOVX @DPTR, A
3
DPTR, #data16
2
0
—
1
Load the Data Pointer with a 16-bit
constant.
Move code byte relative to DPTR to the
accumulator.
Move data byte the accumulator to data
memory relative to DPTR.
Move data byte from data memory
relative to DPTR to the accumulator.
DPS
0
P87LPC764
Reset Value: 00h
SU01184
Product data