ST72F63BK6M1 STMicroelectronics, ST72F63BK6M1 Datasheet - Page 111
ST72F63BK6M1
Manufacturer Part Number
ST72F63BK6M1
Description
MCU 8BIT LS USB 32KB FLSH 34SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F63BD6U1TR.pdf
(186 pages)
Specifications of ST72F63BK6M1
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
34-SOIC (7.5mm Width)
Processor Series
ST72F6x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SCI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
19
Number Of Timers
1
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDTU3-EPB/US, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
Minimum Operating Temperature
0 C
On-chip Adc
8 bit, 8 Channel / 8 bit, 12 Channel
For Use With
497-8428 - BOARD EVAL CHARGER ST7260/L6924D497-5521 - EVAL BOARD LOW SPEED USB497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5625-5
Available stocks
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ST7263Bxx
11.5.4
When the I²C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.
Figure 47. I²C interface block diagram
Functional description
Refer to the CR, SR1 and SR2 registers in
By default the I²C interface operates in Slave mode (M/SL bit is cleared) except when it
initiates a transmit or receive sequence.
Slave mode
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register; then it is compared with the address of the interface or the General Call
address (if selected by software).
●
●
Then the interface waits for a read of the SR1 register, holding the SCL line low (see
Figure 48
Next, software must read the DR register to determine from the least significant bit (Data
Direction Bit) if the slave must enter Receiver or Transmitter mode.
Slave receiver
SCL or SCLI
SDA or SDAI
Address not matched: the interface ignores it and waits for another Start condition.
Address matched
The interface generates in sequence:
–
–
Acknowledge pulse if the ACK bit is set.
EVF and ADSL bits are set with an interrupt if the ITE bit is set.
Transfer sequencing EV1).
CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
DATA CONTROL
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL REGISTER (CR)
Doc ID 7516 Rev 8
Section
OWN ADDRESS REGISTER (OAR)
DATA SHIFT REGISTER
DATA REGISTER (DR)
CONTROL LOGIC
11.5.7. for the bit definitions.
COMPARATOR
INTERRUPT
On-chip peripherals
111/186
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