ST72F63BK6M1 STMicroelectronics, ST72F63BK6M1 Datasheet - Page 63
![MCU 8BIT LS USB 32KB FLSH 34SOIC](/photos/12/15/121510/497-34-soic_series_sml.jpg)
ST72F63BK6M1
Manufacturer Part Number
ST72F63BK6M1
Description
MCU 8BIT LS USB 32KB FLSH 34SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F63BD6U1TR.pdf
(186 pages)
Specifications of ST72F63BK6M1
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
34-SOIC (7.5mm Width)
Processor Series
ST72F6x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SCI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
19
Number Of Timers
1
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDTU3-EPB/US, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
Minimum Operating Temperature
0 C
On-chip Adc
8 bit, 8 Channel / 8 bit, 12 Channel
For Use With
497-8428 - BOARD EVAL CHARGER ST7260/L6924D497-5521 - EVAL BOARD LOW SPEED USB497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5625-5
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Price
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ST7263Bxx
Input Capture
In this section, the index, i, may be 1 or 2 because there are two input capture functions in
the 16-bit timer.
The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value of the
free running counter after a transition is detected on the ICAPi pin (see
Table 19.
ICiR register is a read-only register.
The active transition is software programmable through the IEDGi bit of Control registers
(CRi).
Timing resolution is one count of the free running counter: (
Procedure
To use the input capture function select the following in the CR2 register:
1.
2.
3.
When an input capture occurs:
●
●
●
Clearing the input Capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
1.
2.
Select the timer clock (CC[1:0]) (see
Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2
pin must be configured as floating input or input with pull-up without interrupt if this
configuration is available).
Select the following in the CR1 register:
a)
b)
ICFi bit is set.
The ICiR register contains the value of the free running counter on the active transition
on the ICAPi pin (see
A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC
register. Otherwise, the interrupt remains pending until both conditions become true.
Reading the SR register while the ICFi bit is set.
An access (read or write) to the ICiLR register.
Set the ICIE bit to generate an interrupt after an input capture coming from either
the ICAP1 pin or the ICAP2 pin
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1pin must be configured as floating input or input with pull-up without
interrupt if this configuration is available).
ICiR
IC/R register
Figure
Doc ID 7516 Rev 8
33).
MS Byte
ICiHR
Table
24).
f
CPU
/
CC[1:0]).
On-chip peripherals
LS Byte
Figure
ICiLR
32).
63/186
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