STM32F103C8T6TR STMicroelectronics, STM32F103C8T6TR Datasheet - Page 38

• Manufacturer Part Number: STM32F103C8T6TR
• Description: MCU ARM 64KB FLASH MEM 48-LQFP
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F103C8T6TR

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• For Use With: 497-10048 - BOARD EVAL ACCELEROMETER497-10030 - STARTER KIT FOR STM32497-8511 - KIT STARTER FOR STM32 512K FLASH497-6438 - BOARD EVALUTION FOR STM32 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Electrical characteristics
5.3.8
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Wakeup time from low power mode
The wakeup times given in
oscillator. The clock source used to wake up the device depends from the current operating
mode:
All timings are derived from tests performed under ambient temperature and V
voltage conditions summarized in
Table 21.
1. TBD stands for to be determined.
2. The wakeup time from Sleep and Stop mode are measured from the wakeup event to the point in which the
3. The wakeup time from Standby mode is measured from the wakeup event to the point in which the device
PLL characteristics
The parameters given in
temperature and V
Table 22.
1. TBD stands for to be determined.
2. Data based on device characterization, not tested in production.
t
t
t
WUSTDBY
WUSLEEP
f
WUSTOP
Symbol
PLL_OUT
Symbol
f
t
t
JITTER
PLL_IN
user application code reads the first instruction.
exits from reset.
f
LOCK
VCO
Stop or Standby mode: the clock source is the RC oscillator
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
(2)
(2)
(3)
PLL input clock
PLL input clock duty cycle
PLL multiplier output clock
VCO frequency range
PLL lock time
Cycle to cycle jitter (+/-3
peak to peak)
Low-power mode wakeup timings
Wakeup from Sleep mode
Wakeup from Stop mode
(regulator in run mode)
Wakeup from Stop mode
(regulator in low power mode)
Wakeup from Standby mode
PLL characteristics
DD
Parameter
Parameter
supply voltage conditions summarized in
Table 22
Table 21
(1)
Table
are derived from tests performed under ambient
is measured on a wakeup phase with a 8-MHz HSI RC
When PLL operates
(locked)
V
DD
Test Conditions
7.
is stable
Wakeup on HSI RC clock
HSI RC wakeup time = 2 µs
HSI RC wakeup time = 2 µs,
Regulator wakeup from LP
mode time = 5 µs
HSI RC wakeup time = 2 µs,
Regulator wakeup from power
down time = 38 µs
(1)
Conditions
TBD
Min
40
16
32
Table
Typ
8.0
Value
7.
0.75
Typ
40
4
7
Max
TBD
STM32F103xx
144
200
60
72
DD
(2)
TBD
TBD
TBD
TBD
Max
supply
MHz
MHz
MHz
Unit
µs
Unit
%
%
µs
µs
µs