STM32F103C8T6TR STMicroelectronics, STM32F103C8T6TR Datasheet - Page 49

• Manufacturer Part Number: STM32F103C8T6TR
• Description: MCU ARM 64KB FLASH MEM 48-LQFP
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F103C8T6TR

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• For Use With: 497-10048 - BOARD EVAL ACCELEROMETER497-10030 - STARTER KIT FOR STM32497-8511 - KIT STARTER FOR STM32 512K FLASH497-6438 - BOARD EVALUTION FOR STM32 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

STM32F103xx
5.3.15
Communications interfaces
I
Unless otherwise specified, the parameters given in
performed under ambient temperature, f
summarized in
The STM32F103xx performance line I
I
mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and V
diode between the I/O pin and V
connected to the I
master node remains powered on. Otherwise, the STM32F103xx would be powered by the
protection diode.
The I
characteristics
and SCL) .
Table 34.
1. Values based on standard I
2. f
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
2
2
t
C communication protocol with the following restrictions: the I/O pins SDA and SCL are
C interface characteristics
w(STO:STA)
Symbol
t
t
t
t
t
w(SCLH)
w(SCLL)
t
su(SDA)
t
t
t
su(STO)
higher than 4 MHz to achieve the maximum fast mode I
period of SCL signal.
undefined region of the falling edge of SCL.
t
t
su(STA)
h(SDA)
PCLK1
r(SDA)
r(SCL)
f(SDA)
h(STA)
f(SCL)
C
2
C characteristics are described in
b
must be higher than 2 MHz to achieve the maximum standard mode I
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Repeated Start condition
setup time
Stop condition setup time
Stop to Start condition time
(bus free)
Capacitive load for each bus
line
I
2
C characteristics
for more details on the input/output alternate function characteristics (SDA
Table
2
C bus, it is not possible to power off the STM32F103xx while another I
Parameter
7.
2
DD
C protocol requirement, not tested in production.
is disabled, but is still present. In addition, there is a protection
DD
. As a consequence, when multiple master devices are
2
C interface meets the requirements of the standard
Standard mode I
PCLK1
Table
Min
250
0
4.7
4.0
4.0
4.7
4.0
4.7
(3)
frequency and V
34. Refer also to
2
C frequency.
Table 34
1000
Max
300
400
2
C
(1)
are derived from tests
20 + 0.1C
20 + 0.1C
DD
Section 5.3.12: I/O port pin
Fast mode I
2
Electrical characteristics
Min
100
C frequency. It must be
0
1.3
0.6
0.6
0.6
0.6
1.3
supply voltage conditions
(4)
b
b
2
C
900
Max
300
300
400
(1)(2)
(3)
Unit
µs
ns
µs
pF
49/67
s
s
2
C