ST72F561AR6T3 STMicroelectronics, ST72F561AR6T3 Datasheet - Page 222

• Manufacturer Part Number: ST72F561AR6T3
• Description: IC MCU 8BIT 32K FLASH 64-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561AR6T3

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST72561
12.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for T
Notes:
1. Data based on characterization results, not tested in production.
12.3.3 Auxiliary Voltage Detector (AVD) Thresholds
Subject to general operating conditions for T
1. Data based on characterization results, not tested in production.
Figure 120. LVD Startup Behavior
Note: When the LVD is enabled, the MCU reaches its authorized operating voltage from a reset state.
However, in some devices, the reset signal may be undefined until V
quence, the I/Os may toggle when V
Because Flash write access is impossible below this voltage, the Flash memory contents will not be cor-
rupted.
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V
V
V
Vt
t
V
V
V
ΔV
g(VDD)
Symbol
Symbol
IT+(LVD)
IT-(LVD)
hys(LVD)
IT+(AVD)
IT-(AVD)
hys(AVD)
POR
IT-
Reset state
not defined
in this area
Reset release threshold (V
Reset generation threshold (V
LVD voltage threshold hysteresis
V
V
LVD
1⇒0 AVDF flag toggle threshold
(V
0⇒1 AVDF flag toggle threshold
(V
AVD voltage threshold hysteresis
Voltage drop between AVD flag set
and LVD reset activated
DD
DD
DD
DD
1)
glitches filtered (not detected) by
rise time rate
rise)
fall)
2V
5V
V
Parameter
Parameter
IT+
1)
DD
DD
DD
rise)
is below this voltage.
1)
fall)
A
A
V
V
V
Measured at V
.
.
IT+(AVD)
IT-(AVD)
IT+(LVD)
-V
Conditions
-V
Conditions
-V
IT-(LVD)
IT-(AVD)
IT-(LVD)
IT-(LVD)
DD
is approximately 2V. As a conse-
4.0
4.4
Min
150
Min
3.8
4.2
6
1)
1)
t
Typ
Typ
200
250
450
4.2
4.0
4.6
4.4
LVD RESET
4.25
4.65
Max
Max
250
100
4.5
4.9
40
1)
1)
ms/V
Unit
μs/V
Unit
mV
mV
ns
V
V