ST7FDALIF2M6 STMicroelectronics, ST7FDALIF2M6 Datasheet - Page 109
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ST7FDALIF2M6
Manufacturer Part Number
ST7FDALIF2M6
Description
IC MCU 8BIT 8K 20-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7DALI-EVAL.pdf
(171 pages)
Specifications of ST7FDALIF2M6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
DALI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ST7DALI
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
DALI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
15
Number Of Timers
4 bit
Operating Supply Voltage
2.4 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7DALI-EVAL, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
For Use With
497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-2131-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST7FDALIF2M6TR
Manufacturer:
NEC
Quantity:
670
ST7DALIF2
17.6
Note:
17.7
17.7.1
Note:
Interrupts
Table 47.
The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
Register description
Control register (SPICR)
Read/Write
Reset Value: 0000 xxxx (0xh)
Bit 7 = SPIE Serial Peripheral Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End of Transfer event, Master Mode Fault or
Overrun error occurs (SPIF=1, MODF=1 or OVR=1 in the SPICSR register)
Bit 6 = SPE Serial Peripheral Output Enable.
This bit is set and cleared by software. It is also cleared by hardware when, in master mode,
SS=0 (see
SPI peripheral is not initially connected to the external pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Bit 5 = SPR2 Divider Enable.
This bit is set and cleared by software and is cleared by reset. It is used with the SPR[1:0]
bits to set the baud rate. Refer to
0: Divider by 2 enabled
1: Divider by 2 disabled
This bit has no effect in slave mode.
SPI End of Transfer Event
Master Mode Fault Event
Overrun Error
SPIE
7
Interrupt Event
Master mode fault (MODF) on page
Interrupt control bits
SPE
SPR2
Table 48: SPI master mode SCK
MSTR
MODF
Event
SPIF
OVR
Flag
CPOL
105). The SPE bit is cleared by reset, so the
Control
Enable
SPIE
Bit
Serial peripheral interface (SPI)
CPHA
from
Wait
Exit
frequency.
Yes
Yes
Yes
SPR1
from
Exit
Halt
Yes
No
No
SPR0
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