ST7FDALIF2M6 STMicroelectronics, ST7FDALIF2M6 Datasheet - Page 78

• Manufacturer Part Number: ST7FDALIF2M6
• Description: IC MCU 8BIT 8K 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FDALIF2M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: DALI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7DALI
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: DALI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7DALI-EVAL, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2131-5

12-bit autoreload timer 2 (AT2)
14.6.2
14.6.3
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Bits 4:3 = CK[1:0] Counter Clock Selection.
These bits are set and cleared by software and cleared by hardware after a reset. They
select the clock frequency of the counter.
Table 38.
1. PWM mode and Output Compare modes are not available at this frequency.
2. ATICR counter may return inaccurate results when read. It is therefore not recommended to use Input
Bit 2 = OVF Overflow Flag.
This bit is set by hardware and cleared by software by reading the TCSR register. It
indicates the transition of the counter from FFFh to ATR value.
0: No counter overflow occurred
1: Counter overflow occurred
Bit 1 = OVFIE Overflow Interrupt Enable.
This bit is read/write by software and cleared by hardware after a reset.
0: OVF interrupt disabled.
1: OVF interrupt enabled.
Bit 0 = CMPIE Compare Interrupt Enable.
This bit is read/write by software and cleared by hardware after a reset. It can be used to
mask the interrupt generated when the CMPF bit is set.
0: CMPF interrupt disabled.
1: CMPF interrupt enabled.
Counter register high (CNTRH)
Read only
Reset Value: 0000 0000 (000h)
Counter register low (CNTRL)
Read only
Reset Value: 0000 0000 (000h)
Bits 15:12 = Reserved.
Bits 11:0 = CNTR[11:0] Counter Value.
This 12-bit register is read by software and cleared by hardware after a reset. The counter is
incremented continuously as soon as a counter clock is selected. To obtain the 12-bit value,
CNTR7
Capture mode at this frequency.
15
0
7
Counter clock frequency
CNTR6
0
f
LTIMER
Counter clock selection
(1 ms timebase @ 8 MHz)
CNTR5
0
32 MHz
OFF
f
CPU
(2)
CNTR4
0
CNTR3
(1)
CNTR
11
CNTR2
CNTR
10
CNTR9
CNTR1
CK1
0
0
1
1
ST7DALIF2
CNTR8
CNTR0
CK0
0
1
0
1
8
0