ST7FDALIF2M6 STMicroelectronics, ST7FDALIF2M6 Datasheet - Page 76

IC MCU 8BIT 8K 20-SOIC

ST7FDALIF2M6

Manufacturer Part Number
ST7FDALIF2M6
Description
IC MCU 8BIT 8K 20-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST7FDALIF2M6

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
DALI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ST7DALI
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
DALI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
15
Number Of Timers
4 bit
Operating Supply Voltage
2.4 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7DALI-EVAL, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
For Use With
497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-2131-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST7FDALIF2M6
Quantity:
4 000
Part Number:
ST7FDALIF2M6TR
Manufacturer:
NEC
Quantity:
670
12-bit autoreload timer 2 (AT2)
14.3.4
76/171
Figure 37. Block diagram of break function
Input capture
The 12-bit ATICR register is used to latch the value of the 12-bit free running upcounter after
a rising or falling edge is detected on the ATIC pin. When an input capture occurs, the ICF
bit is set and the ATICR register contains the value of the free running upcounter. An IC
interrupt is generated if the ICIE bit is set. The ICF bit is reset by reading the ATICR register
when the ICF bit is set. The ATICR is a read only register and always contains the free
running upcounter value which corresponds to the most recent input capture. Any further
input capture is inhibited while the ICF bit is set.
Figure 38. Input capture timing diagram
BREAK pin
Note:
The BREAK pin value is latched by the BA bit.
ICR REGISTER
COUNTER
ICF FLAG
f
ATIC PIN
COUNTER
(Active Low)
01h
BA
PWM2
PWM3
PWM0
PWM1
BPEN
02h
xxh
PWM3
03h
BREAKCR Register
PWM2
04h
(Inverters)
PWM1
05h
INTERRUPT
PWM0
06h
07h
04h
1
0
When BA is set:
PWM counter -> Reset value
ARR & DCRx -> Reset value
PWM Mode -> Reset value
08h
ATICR READ
09h
0Ah
09h
PWM0
PWM1
PWM2
PWM3
INTERRUPT
ST7DALIF2
t

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