ST72F561R9TA STMicroelectronics, ST72F561R9TA Datasheet - Page 113
ST72F561R9TA
Manufacturer Part Number
ST72F561R9TA
Description
IC MCU 8BIT 60K FLASH 64-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F561K6T6.pdf
(265 pages)
Specifications of ST72F561R9TA
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
For Use With
497-8374 - BOARD DEVELOPMENT FOR ST72F561
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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SERIAL PERIPHERAL INTERFACE (cont’d)
10.6.3.2 Slave Select Management
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
In Master mode:
Figure 72. Generic SS Timing Diagram
Figure 73. Hardware/Software Slave Select Management
– SS internal must be held high continuously
Figure
(if CPHA = 0)
(if CPHA = 1)
MOSI/MISO
Master SS
Slave SS
Slave SS
73).
SS external pin
SSI bit
Byte 1
SSM bit
1
0
In Slave Mode:
There are two cases depending on the data/clock
timing relationship (see
If CPHA = 1 (data latched on second clock edge):
If CPHA = 0 (data latched on first clock edge):
– SS internal must be held low during the entire
– SS internal must be held low during byte
Byte 2
SS internal
transmission. This implies that in single slave
applications the SS pin either can be tied to
V
ing the SS function by software (SSM = 1 and
SSI = 0 in the in the SPICSR register)
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see
SS
, or made free for standard I/O by manag-
Byte 3
Section
Figure
10.6.5.3).
72):
ST72561
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