ST72F561R9TA STMicroelectronics, ST72F561R9TA Datasheet - Page 99
ST72F561R9TA
Manufacturer Part Number
ST72F561R9TA
Description
IC MCU 8BIT 60K FLASH 64-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F561K6T6.pdf
(265 pages)
Specifications of ST72F561R9TA
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
For Use With
497-8374 - BOARD DEVELOPMENT FOR ST72F561
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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8-BIT TIMER (Cont’d)
Notes:
1. Once the OCIE bit is set both output compare
2. If the OCiE bit is not set, the OCMPi pin is a
3. When the timer clock is f
4. The output compare functions can be used both
5. The value in the 8-bit OC
Figure 65. Output Compare Block Diagram
8-bit
features may trigger interrupt requests. If only
one is needed in the application, the interrupt
routine software needs to discard the unwanted
compare interrupt. This can be done by check-
ing the OCF1 and OCF2 flags and resetting
them both.
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
OCMPi are set while the counter value equals
the OCiR register value (see
99). This behaviour is the same in OPM or
PWM mode.
When the timer clock is f
8000, OCFi and OCMPi are set while the coun-
ter value equals the OCiR register value plus 1
(see
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
OLVi bit should be changed after each suc-
8 BIT
OC1R Register
OUTPUT COMPARE
8-bit
Figure 67 on page
CIRCUIT
OC2R Register
FREE RUNNING
COUNTER
8-bit
99).
CPU
i
R register and the
CPU
Figure 66 on page
/4, f
/2, OCFi and
OC1E
CPU
/8 or f
OCIE
OC2E
OCF1
CPU
/
FOLV2 FOLV1
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit = 1). The OCFi bit is then
not set by hardware, and thus no interrupt request
is generated.
The FOLVLi bits have no effect in both one pulse
mode and PWM mode.
(Control Register 2) CR2
(Control Register 1) CR1
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
OCF2
CC1
(Status Register) SR
OLVL2
CC0
0
0
OLVL1
0
Latch
Latch
1
2
ST72561
OCMP1
OCMP2
Pin
Pin
99/265
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