ST72F561R9TA STMicroelectronics, ST72F561R9TA Datasheet - Page 143
ST72F561R9TA
Manufacturer Part Number
ST72F561R9TA
Description
IC MCU 8BIT 60K FLASH 64-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F561K6T6.pdf
(265 pages)
Specifications of ST72F561R9TA
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
For Use With
497-8374 - BOARD DEVELOPMENT FOR ST72F561
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
10.7.9.5 LIN Baud Rate
Baud rate programming is done by writing a value
in the LPR prescaler or performing an automatic
resynchronization as described below.
Automatic Resynchronization
To automatically adjust the baud rate based on
measurement of the LIN Synch Field:
– Write the nominal LIN Prescaler value (usually
– Set the LASE bit to enable the Auto Synchroni-
When Auto Synchronization is enabled, after each
LIN Synch Break, the time duration between five
falling edges on RDI is sampled on f
result of this measurement is stored in an internal
15-bit register called SM (not user accessible)
(see
ciated LPFR and LPR registers) are automatically
updated at the end of the fifth falling edge. During
LIN Synch field measurement, the SCI state ma-
chine is stopped and no data is transferred to the
data register.
10.7.9.6 LIN Slave Baud Rate Generation
In LIN mode, transmission and reception are driv-
en by the LIN baud rate generator
Note: LIN Master mode uses the Extended or
Conventional prescaler register to generate the
baud rate.
If LINE bit = 1 and LSLV bit = 1 then the Conven-
tional and Extended Baud Rate Generators are
disabled: the baud rate for the receiver and trans-
depending on the nominal baud rate) in the
LPFR / LPR registers.
zation Unit.
Figure
7). Then the LDIV value (and its asso-
CPU
and the
mitter are both set to the same value, depending
on the LIN Slave baud rate generator:
with:
LDIV is an unsigned fixed point number. The man-
tissa is coded on 8 bits in the LPR register and the
fraction is coded on 4 bits in the LPFR register.
If LASE bit = 1 then LDIV is automatically updated
at the end of each LIN Synch Field.
Three registers are used internally to manage the
auto-update of the LIN divider (LDIV):
- LDIV_NOM (nominal value written by software at
LPR/LPFR addresses)
- LDIV_MEAS (results of the Field Synch meas-
urement)
- LDIV (used to generate the local baud rate)
The control and interactions of these registers, ex-
plained in
LDUM bit setting (LIN Divider Update Method).
Note:
As explained in
be updated by two concurrent actions: a transfer
from LDIV_MEAS at the end of the LIN Sync Field
and a transfer from LDIV_NOM due to a software
write of LPR. If both operations occur at the same
time, the transfer from LDIV_NOM has priority.
Figure 8
Tx = Rx =
Figure 8
and
(16
Figure
f
CPU
and
*
LDIV)
Figure
9, depend on the
9, LDIV can
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