ST72F561R9TA STMicroelectronics, ST72F561R9TA Datasheet - Page 259

• Manufacturer Part Number: ST72F561R9TA
• Description: IC MCU 8BIT 60K FLASH 64-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561R9TA

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

IMPORTANT NOTES (Cont’d)
software sequence is given for both cases (global
interrupt disabled/enabled).
Case 1: Writing to PxOR or PxDDR with Global In-
terrupts Enabled:
LD A,#01
LD sema,A
LD A,PFDR
AND A,#02
LD X,A
PxOR/PxDDR
LD A,#$90
LD PFDDR,A ; Write to PFDDR
LD A,#$ff
LD PFOR,A
LD A,PFDR
AND A,#02
LD Y,A
PxOR/PxDDR
LD A,X
cp A,#02
jrne OUT
TNZ Y
jrne OUT
LD A,sema
edge is detected
CP A,#01
jrne OUT
call call_routine; call the interrupt routine
OUT:LD A,#00
LD sema,A
.call_routine
PUSH A
PUSH X
PUSH CC
.ext1_rt
LD A,#00
LD sema,A
IRET
Case 2: Writing to PxOR or PxDDR with Global In-
terrupts Disabled:
SIM
LD A,PFDR
AND A,#$02
; set the interrupt mask
; set the semaphore to '1'
; store the level before writing to
; store the level after writing to
; check for falling edge
; check the semaphore status if
; entry to call_routine
; entry to interrupt routine
; Write to PFOR
LD X,A
PxOR/PxDDR
LD A,#$90
LD PFDDR,A; Write into PFDDR
LD A,#$ff
LD PFOR,A
LD A,PFDR
AND A,#$02
LD Y,A
PxDDR
LD A,X
cp A,#$02
jrne OUT
TNZ Y
jrne OUT
LD A,#$01
LD sema,A ; set the semaphore to '1' if edge is
detected
RIM
LD A,sema ; check the semaphore status
CP A,#$01
jrne OUT
call call_routine; call the interrupt routine
RIM
OUT:
JP while_loop
.call_routine ; entry to call_routine
PUSH A
PUSH X
PUSH CC
.ext1_rt
LD A,#$00
LD sema,A
IRET
16.1.4 Unexpected Reset Fetch
If an interrupt request occurs while a "POP CC" in-
struction is executed, the interrupt controller does
not recognise the source of the interrupt and, by
default, passes the RESET vector address to the
CPU.
Workaround
To solve this issue, a "POP CC" instruction must
always be preceded by a "SIM" instruction.
; store the level before writing to
; store the level after writing to PxOR/
; check for falling edge
RIM
; entry to interrupt routine
; reset the interrupt mask
; Write to PFOR
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