ST72F521AR9TC STMicroelectronics, ST72F521AR9TC Datasheet - Page 38

• Manufacturer Part Number: ST72F521AR9TC
• Description: IC MCU 8BIT 60K FLASH 64-TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F521AR9TC

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: 497-6453 - BOARD EVAL BASED ON ST7LNBX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST72F521, ST72521B
INTERRUPTS (Cont’d)
Table 7. Interrupt Mapping
Notes:
1. Exit from HALT possible when SPI is in slave mode.
2. Exit from HALT possible when PWM ART is in external clock mode.
3. In Flash devices only a RESET or MCC/RTC interrupt can be used to wake-up from Active Halt mode.
7.6 EXTERNAL INTERRUPTS
7.6.1 I/O Port Interrupt Sensitivity
The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the EICR register
(Figure
independent external interrupt source sensitivities.
Each external interrupt source can be generated
on four (or five) different events on the pin:
■
■
■
38/215
N°
10
11
12
13
Falling edge
Rising edge
Falling and rising edge
0
1
2
3
4
5
6
7
8
9
22). This control allows to have up to 4 fully
MCC/RTC
PWM ART
TIMER A
TIMER B
Source
RESET
Block
TRAP
CAN
AVD
SCI
SPI
I2C
TLI
ei0
ei1
ei2
ei3
Reset
Software interrupt
External top level interrupt
Main clock controller time base interrupt
External interrupt port A3..0
External interrupt port F2..0
External interrupt port B3..0
External interrupt port B7..4
CAN peripheral interrupts
SPI peripheral interrupts
TIMER A peripheral interrupts
TIMER B peripheral interrupts
SCI Peripheral interrupts
Auxiliary Voltage detector interrupt
I2C Peripheral interrupts
PWM ART interrupt
Description
■
■
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). This means that interrupts must
be disabled before changing sensitivity.
The pending interrupts are cleared by writing a dif-
ferent value in the ISx[1:0], IPA or IPB bits of the
EICR.
Falling edge and low level
Rising edge and high level (only for ei0 and ei2)
(see periph)
ARTCSR
Register
CANISR
MCCSR
SPICSR
SCISR
SICSR
Label
TASR
TBSR
EICR
N/A
N/A
Priority
Priority
Priority
Higher
Order
Lower
ACTIVE
HALT
HALT/
from
yes
yes
Exit
yes
yes
yes
yes
yes
yes
yes
yes
no
no
no
no
no
no
1
2
3)
FFECh-FFEDh
FFFCh-FFFDh
FFEEh-FFEFh
FFEAh-FFEBh
FFFEh-FFFFh
FFFAh-FFFBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
Address
Vector