ST72F521AR9TC STMicroelectronics, ST72F521AR9TC Datasheet - Page 58

IC MCU 8BIT 60K FLASH 64-TQFP

ST72F521AR9TC

Manufacturer Part Number
ST72F521AR9TC
Description
IC MCU 8BIT 60K FLASH 64-TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST72F521AR9TC

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TQFP, 64-VQFP
For Use With
497-6453 - BOARD EVAL BASED ON ST7LNBX
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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ST72F521, ST72521B
10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)
The Main Clock Controller consists of three differ-
ent functions:
Each function can be used independently and si-
multaneously.
10.2.1 Programmable CPU Clock Prescaler
The programmable CPU clock prescaler supplies
the clock for the ST7 CPU and its internal periph-
erals. It manages SLOW power saving mode (See
Section 8.2 SLOW MODE
The prescaler selects the f
cy and is controlled by three bits in the MCCSR
register: CP[1:0] and SMS.
10.2.2 Clock-out Capability
The clock-out capability is an alternate function of
an I/O port pin that outputs a f
Figure 35. Main Clock Controller (MCC/RTC) Block Diagram
58/215
f
OSC2
a programmable CPU clock prescaler
a clock-out signal to supply external devices
a real time clock timer with interrupt capability
MCCBCR
MCCSR
DIV 2, 4, 8, 16
MCO
CP1 CP0
CPU
DIV 64
for more details).
main clock frequen-
CPU
SMS
1
0
clock to drive
BEEP SIGNAL
12-BIT MCC RTC
SELECTION
TB1 TB0 OIE
COUNTER
BC1 BC0
external devices. It is controlled by the MCO bit in
the MCCSR register.
CAUTION: When selected, the clock out pin sus-
pends the clock during ACTIVE-HALT mode.
10.2.3 Real Time Clock Timer (RTC)
The counter of the real time clock timer allows an
interrupt to be generated based on an accurate
real time clock. Four different time bases depend-
ing directly on f
functionality is controlled by four bits of the MCC-
SR register: TB[1:0], OIE and OIF.
When the RTC interrupt is enabled (OIE bit set),
the ST7 enters ACTIVE-HALT mode when the
HALT instruction is executed. See
TIVE-HALT AND HALT MODES
10.2.4 Beeper
The beep function is controlled by the MCCBCR
register. It can output three selectable frequencies
on the BEEP pin (I/O port alternate function).
OIF
MCC/RTC INTERRUPT
f
CPU
WATCHDOG
TIMER
TO
OSC2
are available. The whole
PERIPHERALS
for more details.
TO CPU AND
CPU CLOCK
BEEP
MCO
Section 8.4 AC-

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