STM32F107VCT6 STMicroelectronics, STM32F107VCT6 Datasheet - Page 19

• Manufacturer Part Number: STM32F107VCT6
• Description: MCU ARM 256KB FLASH MEM 100-LQFP
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F107VCT6

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, LIN, SPI, UART/USART, USB OTG
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 80
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: STM32F107x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: CAN, I2C, SPI, USART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 10
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit x 2, 16 Channel
• On-chip Dac: 12 bit x 2, 2 Channel
• For Use With: 497-10591 - DAUGHTER BOARD FOR STM32497-10064 - EVAL BOARD497-9040 - DEV KIT FOR STM32497-9041 - DEV KIT FOR STM32497-9042 - DEV KIT FOR STM32497-9043 - DEV KIT FOR STM32497-8924 - EVAL BOARD FOR STM32F107VCT497-8853 - BOARD DEMO STM32 UNIV USB-UUSCI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-8913

STM32F105xx, STM32F107xx
2.3.18
2.3.19
2.3.20
USART1, USART2 and USART3 also provide hardware management of the CTS and RTS
signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All
interfaces can be served by the DMA controller except for UART5.
Serial peripheral interface (SPI)
Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in
full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC/SDHC
All SPIs can be served by the DMA controller.
Inter-integrated sound (I
Two standard I
operated in master or slave mode. These interfaces can be configured to operate with 16/32
bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to
96 kHz are supported. When either or both of the I
mode, the master clock can be output to the external DAC/CODEC at 256 times the
sampling frequency with less than 0.5% accuracy error owing to the advanced clock
controller (see
Please refer to the “Audio frequency precision” tables provided in the “Serial peripheral
interface (SPI)” section of the STM32F10xxx reference manual.
Ethernet MAC interface with dedicated DMA and IEEE 1588 support
Peripheral not available on STM32F105xx devices.
The STM32F107xx devices provide an IEEE-802.3-2002-compliant media access controller
(MAC) for ethernet LAN communications through an industry-standard media-independent
interface (MII) or a reduced media-independent interface (RMII). The STM32F107xx
requires an external physical interface device (PHY) to connect to the physical LAN bus
(twisted-pair, fiber, etc.). the PHY is connected to the STM32F107xx MII port using as many
as 17 signals (MII) or 9 signals (RMII) and can be clocked using the 25 MHz (MII) or 50 MHz
(RMII) output from the STM32F107xx.
The STM32F107xx includes the following features:
●
●
●
●
●
a. SDHC = Secure digital high capacity.
Supports 10 and 100 Mbit/s rates
Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors (see the STM32F105xx/STM32F107xx reference manual for
details)
Tagged MAC frame support (VLAN support)
Half-duplex (CSMA/CD) and full-duplex operation
MAC control sublayer (control frames) support
2
Section 2.3.7: Clocks and
S interfaces (multiplexed with SPI2 and SPI3) are available, that can be
Doc ID 15274 Rev 5
2
S)
startup).
2
S interfaces is/are configured in master
(a)
modes.
Description
19/101