ST10F276-6QR3 STMicroelectronics, ST10F276-6QR3 Datasheet - Page 86

• Manufacturer Part Number: ST10F276-6QR3
• Description: MCU 16BIT 832K FLASH 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276-6QR3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 64MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

General purpose timer unit
10.2
Table 48.
Table 49.
86/231
Prescaler factor
Input frequency
Resolution
Period maximum
Prescaler factor
Input frequency
Resolution
Period maximum
f
f
CPU
CPU
= 40MHz
= 64MHz
GPT2
The GPT2 module provides precise event control and time measurement. It includes two
timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an
input clock which is derived from the CPU clock via a programmable prescaler or with
external signals. The count direction (up/down) for each timer is programmable by software
or may additionally be altered dynamically by an external signal on a port pin (TxEUD).
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5, or it may be output on a port pin
(T6OUT). The overflow / underflow of timer T6 can additionally be used to clock the
CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL
register may capture the contents of timer T5 based on an external signal transition on the
corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture
procedure. This allows absolute time differences to be measured or pulse multiplication to
be performed without software overhead.
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1
timer T3 inputs T3IN and/or T3EUD. This is advantageous when T3 operates in Incremental
Interface Mode.
Table 48
scaler option at 40 MHz and 64 MHz CPU clock respectively.
GPT2 timer input frequencies, resolutions and periods at 40 MHz
GPT2 timer input frequencies, resolutions and periods at 64 MHz
10 MHz
16 MHz
6.55ms
62.5ns
100ns
4.1ms
000b
000b
and
4
4
Table 49
13.1ms
5 MHz
200ns
8 MHz
125ns
8.2ms
001b
001b
8
8
list the timer input frequencies, resolution and periods for each pre-
2.5 MHz
26.2ms
16.4ms
400ns
4 MHz
250ns
010b
010b
16
16
Timer input selection T5I / T6I
Timer input selection T5I / T6I
1.25 MHz
52.4ms
32.8ms
2 MHz
0.8µs
011b
0.5µs
011b
32
32
104.8ms
625 kHz
65.5ms
1.6µs
100b
1 kHz
1.0µs
100b
64
64
312.5 kHz 156.25 kHz 78.125 kHz
209.7ms
131.1ms
500 kHz
3.2µs
101b
2.0µs
128
101b
128
419.4ms
262.1ms
250 kHz
6.4µs
110b
4.0µs
110b
256
256
ST10F276E
838.9ms
524.3ms
128 kHz
12.8µs
111b
8.0µs
111b
512
512