MC908GR4CDWE Freescale Semiconductor, MC908GR4CDWE Datasheet - Page 194

• Manufacturer Part Number: MC908GR4CDWE
• Description: IC MCU 4K FLASH 8MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR4CDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

System Integration Module (SIM)
19.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See
free-running after all reset states. (See
internal reset recovery sequences.)
19.5 Exception Control
Normal, sequential program execution can be changed in three different ways:
19.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume.
interrupt entry timing.
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared). See
194
MODULE INTERRUPT
•
•
•
I BIT
R/W
IDB
IAB
INTERRUPT
MODULE
I BIT
R/W
Interrupts:
–
–
Reset
Break interrupts
IDB
IAB
Maskable hardware CPU interrupts
Non-maskable software interrupt instruction (SWI)
DUMMY
DUMMY
Figure 19-9
SP
SP – 4
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
PC – 1[7:0]
Figure 19-9. Interrupt Recovery Timing
CCR
Figure 19-8
shows interrupt recovery timing.
SP – 1
SP – 3
PC – 1[15:8]
19.3.2 Active Resets from Internal Sources
A
SP – 2
SP – 2
.
Interrupt Entry Timing
X
Figure
X
SP – 3
SP – 1
19.6.2 Stop Mode
PC – 1 [7:0]
19-10.
A
SP – 4
SP
CCR
PC – 1 [15:8]
VECT H
PC
V DATA H
OPCODE
for details.) The SIM counter is
VECT L
PC + 1
V DATA L
OPERAND
Figure 19-8
START ADDR
for counter control and
Freescale Semiconductor
OPCODE
shows