MC908GR4CDWE Freescale Semiconductor, MC908GR4CDWE Datasheet - Page 210

• Manufacturer Part Number: MC908GR4CDWE
• Description: IC MCU 4K FLASH 8MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR4CDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Serial Peripheral Interface (SPI)
Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1. The diagram may
be interpreted as a master or slave timing diagram since the serial clock (SPSCK), master in/slave out
(MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave.
The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS
line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select
input (SS) is at 0, so that only the selected slave drives to the master. The SS pin of the master is not
shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as
general-purpose I/O not affecting the SPI. See
edge is the MSB capture strobe. Therefore, the slave must begin driving its data before the first SPSCK
edge, and a falling edge on the SS pin is used to start the slave data transmission. The slave’s SS pin
must be toggled back to high and then low again between each byte transmitted as shown in
When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the transmission. This
causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from the transmit data register.
Therefore, the SPI data register of the slave must be loaded with transmit data before the falling edge of
SS. Any data written after the falling edge is stored in the transmit data register and transferred to the shift
register after the current transmission.
20.5.3 Transmission Format When CPHA = 1
Figure 20-6
replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing
diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins
are directly connected between the master and the slave. The MISO signal is the output from the slave,
and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The
210
shows an SPI transmission in which CPHA is logic 1. The figure should not be used as a
CAPTURE STROBE
MASTER SS
FOR REFERENCE
SPSCK; CPOL = 0
MISO/MOSI
SPSCK; CPOL =1
SPSCK CYCLE #
SLAVE SS
SLAVE SS
CPHA = 0
CPHA = 1
FROM MASTER
SS; TO SLAVE
FROM SLAVE
MOSI
MISO
Figure 20-4. Transmission Format (CPHA = 0)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
MSB
BYTE 1
Figure 20-5. CPHA/SS Timing
MSB
1
BIT 6
BIT 6
2
20.7.2 Mode Fault
BIT 5
BIT 5
3
BYTE 2
BIT 4
BIT 4
4
BIT 3
BIT 3
5
Error. When CPHA = 0, the first SPSCK
BIT 2
BIT 2
6
BYTE 3
BIT 1
BIT 1
7
LSB
LSB
Freescale Semiconductor
8
Figure
20-5.