MC908GR4CDWE Freescale Semiconductor, MC908GR4CDWE Datasheet - Page 149

• Manufacturer Part Number: MC908GR4CDWE
• Description: IC MCU 4K FLASH 8MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR4CDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

MC68HC908GR8 — Rev 4.0
MOTOROLA
BNE rel
BPL rel
BRA rel
BRCLR n,opr,rel Branch if Bit n in M Clear
BRN rel
BRSET n,opr,rel Branch if Bit n in M Set
BSET n,opr
BSR rel
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
CLC
CLI
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
Source
Form
Branch if Not Equal
Branch if Plus
Branch Always
Branch Never
Set Bit n in M
Branch to Subroutine
Compare and Branch if Equal
Clear Carry Bit
Clear Interrupt Mask
Clear
Operation
Table 10-1. Instruction Set Summary (Continued)
Freescale Semiconductor, Inc.
For More Information On This Product,
Central Processing Unit (CPU)
Go to: www.freescale.com
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
SP
(PC) + 3 + rel ? (A) – (M) = $00
(PC) + 3 + rel ? (A) – (M) = $00
(PC) + 3 + rel ? (X) – (M) = $00
(PC) + 3 + rel ? (A) – (M) = $00
(PC) + 2 + rel ? (A) – (M) = $00
(PC) + 4 + rel ? (A) – (M) = $00
PC
(PC) + 3 + rel ? (Mn) = 0
(PC) + 3 + rel ? (Mn) = 1
(PC) + 2 + rel ? (N) = 0
PC
(PC) + 2 + rel ? (Z) = 0
Description
PC
(SP) – 1; push (PCH)
(PC) + 2; push (PCL)
SP
M
H
M
M
M
A
X
Mn
(PC) + 2 + rel
C
I
(PC) + rel
(PC) + 2
(SP) – 1
$00
$00
$00
$00
$00
$00
$00
0
0
1
V H I N Z C
– – – – – – REL
– – – – – – REL
– – – – – – REL
– – – – –
– – – – – – REL
– – – – –
– – – – – –
– – – – – – REL
– – – – – –
– – – – – 0 INH
– – 0 – – – INH
0 – – 0 1 –
Effect on
CCR
Central Processing Unit (CPU)
Instruction Set Summary
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR
IMM
IMM
IX1+
IX+
SP1
DIR
INH
INH
INH
IX1
IX
SP1
Technical Data
9E6F
9E61
0D
0C
1C
AD
8C
26
2A
20
01
03
05
07
09
0B
0F
21
00
02
04
06
08
0A
0E
10
12
14
16
18
1A
1E
31
41
51
61
71
98
9A
3F
4F
5F
6F
7F
rr
rr
rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd
dd
dd
dd
dd
dd
dd
dd
rr
dd rr
ii rr
ii rr
ff rr
rr
ff rr
dd
ff
ff
149
3
3
3
5
5
5
5
5
5
5
5
3
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
5
4
4
5
4
6
1
2
3
1
1
1
3
2
4