MC908GR4CDWE Freescale Semiconductor, MC908GR4CDWE Datasheet - Page 319

• Manufacturer Part Number: MC908GR4CDWE
• Description: IC MCU 4K FLASH 8MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR4CDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

20.13.1 MISO (Master In/Slave Out)
20.13.2 MOSI (Master Out/Slave In)
MC68HC908GR8 — Rev 4.0
MOTOROLA
communicate with I
when the SPWOM bit in the SPI control register is set. In I
communication, the MOSI and MISO pins are connected to a
bidirectional pin from the I
V
MISO is one of the two SPI module pins that transmits serial data. In full
duplex operation, the MISO pin of the master SPI module is connected
to the MISO pin of the slave SPI module. The master SPI simultaneously
receives data on its MISO pin and transmits data from its MOSI pin.
Slave output data on the MISO pin is enabled only when the SPI is
configured as a slave. The SPI is configured as a slave when its
SPMSTR bit is logic 0 and its SS pin is at logic 0. To support a multiple-
slave system, a logic 1 on the SS pin puts the MISO pin in a high-
impedance state.
When enabled, the SPI controls data direction of the MISO pin
regardless of the state of the data direction register of the shared I/O
port.
MOSI is one of the two SPI module pins that transmits serial data. In full-
duplex operation, the MOSI pin of the master SPI module is connected
to the MOSI pin of the slave SPI module. The master SPI simultaneously
transmits data from its MOSI pin and receives data on its MISO pin.
When enabled, the SPI controls data direction of the MOSI pin
regardless of the state of the data direction register of the shared I/O
port.
DD
Freescale Semiconductor, Inc.
.
For More Information On This Product,
Serial Peripheral Interface (SPI)
Go to: www.freescale.com
2
C peripherals, MOSI becomes an open-drain output
2
C peripheral and through a pullup resistor to
Serial Peripheral Interface (SPI)
2
Technical Data
C
I/O Signals
319