MC908GR4CDWE Freescale Semiconductor, MC908GR4CDWE Datasheet - Page 88

• Manufacturer Part Number: MC908GR4CDWE
• Description: IC MCU 4K FLASH 8MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR4CDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Analog-to-Digital Converter (ADC)
5.8.3 ADC Clock Register
Technical Data
88
Address: $0003E
The ADC clock register (ADCLK) selects the clock frequency for the
ADC.
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADICLK — ADC Input Clock Select Bit
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by
the ADC to generate the internal ADC clock.
available clock configurations. The ADC clock should be set to
approximately 1 MHz.
ADICLK selects either the bus clock or CGMXCLK as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK
as the ADC clock source.
For More Information On This Product,
ADIV2
Bit 7
Analog-to-Digital Converter (ADC)
X = don’t care
0
ADIV2
Go to: www.freescale.com
Figure 5-4. ADC Clock Register (ADCLK)
0
0
0
0
1
= Unimplemented
ADIV1
Table 5-2. ADC Clock Divide Ratio
6
0
ADIV1
0
0
1
1
X
ADIV0
5
0
ADIV0
ADICLK
X
0
1
0
1
4
0
ADC input clock
ADC input clock
ADC input clock
ADC input clock
ADC input clock
3
0
0
ADC Clock Rate
MC68HC908GR8 — Rev 4.0
Table 5-2
2
0
0
1
2
4
8
16
shows the
1
0
0
MOTOROLA
Bit 0
0
0