R5F21257SNFP#U0 Renesas Electronics America, R5F21257SNFP#U0 Datasheet - Page 150

• Manufacturer Part Number: R5F21257SNFP#U0
• Description: IC R8C/25 MCU FLASH 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21257SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
13.2
Table 13.3
NOTES:
Count source
Count operation
Period
Count start condition
Reset condition of watchdog
timer
Count stop condition
Operation at time of underflow
Registers, bits
The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection
mode is enabled. If the CPU clock stops when a program is out of control, the clock can still be supplied to the
watchdog timer.
Table 13.3 lists the Watchdog Timer Specifications (with Count Source Protection Mode Enabled).
1. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address
2. Even if 0 is written to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1.
0FFFFh with a flash programmer.
The CSPROINI bit cannot be changed by a program. To set the CSPROINI bit, write 0 to bit 7 of
address 0FFFFh with a flash programmer.
Count Source Protection Mode Enabled
Feb 29, 2008
Watchdog Timer Specifications (with Count Source Protection Mode Enabled)
Item
Page 131 of 485
Low-speed on-chip oscillator clock
Decrement
Count value of watchdog timer (4096)
Example: Period is approximately 32.8 ms when the low-speed on-
The WDTON bit
of the watchdog timer after a reset.
• When the WDTON bit is set to 1 (watchdog timer is in stop state
• When the WDTON bit is set to 0 (watchdog timer starts
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
None (The count does not stop in wait mode after the count starts.
The MCU does not enter stop mode.)
Watchdog timer reset (Refer to 5.6 Watchdog Timer Reset.)
• When setting the CSPPRO bit in the CSPR register to 1 (count
• The following conditions apply in count source protection mode
Low-speed on-chip oscillator clock
after reset)
automatically after reset)
source protection mode is enabled)
automatically
The watchdog timer and prescaler stop after a reset and the count
starts when the WDTS register is written to
The watchdog timer and prescaler start counting automatically after
a reset
- Set 0FFFh to the watchdog timer
- Set the CM14 bit in the CM1 register to 0 (low-speed on-chip
- Set the PM12 bit in the PM1 register to 1 (The watchdog timer is
- Writing to the CM10 bit in the CM1 register is disabled (It remains
- Writing to the CM14 bit in the CM1 register is disabled (It remains
oscillator on)
reset when watchdog timer underflows)
unchanged even if it is set to 1. The MCU does not enter stop
mode.)
unchanged even if it is set to 1. The low-speed on-chip oscillator
does not stop.)
chip oscillator clock frequency is 125 kHz
(1)
in the OFS register (0FFFFh) selects the operation
Specification
(2)
, the following are set
13. Watchdog Timer