R5F21257SNFP#U0 Renesas Electronics America, R5F21257SNFP#U0 Datasheet - Page 259

• Manufacturer Part Number: R5F21257SNFP#U0
• Description: IC R8C/25 MCU FLASH 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21257SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Figure 14.88
Timer RD Function Control Register
b7 b6 b5 b4
NOTES:
1.
2.
3.
4.
When setting bits CMD1 to CMD0 to 10b or 11b, the MCU enters complementary PWM mode in spite of the setting of
the TRDPMR register.
Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops).
Set the ADCAP bit in the ADC0N0 register to 1 (starts by timer RD).
When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is
enabled.
Feb 29, 2008
b3 b2
TRDFCR Register in Complementary PWM Mode
b1 b0
Bit Symbol
TRDFCR
ADTRG
Symbol
STCLK
ADEG
PWM3
CMD0
CMD1
OLS0
OLS1
Page 240 of 485
Combination mode select bits
Normal-phase output level select bit
(in reset synchronous PWM mode or
complementary PWM mode)
Counter-phase output level select bit
(in reset synchronous PWM mode or
complementary PWM mode)
A/D trigger enable bit
(in complementary PWM mode)
A/D trigger edge select bit
(in complementary PWM mode)
External clock input select bit
PWM3 mode select bit
Address
Bit Name
013Ah
(4)
(1,2)
b1 b0
1 0 : Complementary PWM mode
1 1 : Complementary PWM mode
Other than above : Do not set.
0 : Initial output “H”
1 : Initial output “L”
0 : Initial output “H”
1 : Initial output “L”
0 : Disable A/D trigger
1 : Enable A/D trigger
0 : A/D trigger is generated at
1 : A/D trigger is generated at underflow
0 : External clock input disabled
1 : External clock input enabled
This bit is disabled in complementary PWM
mode.
Active level “L”
Active level “H”
Active level “L”
Active level “H”
compare match betw een registers
TRD0 and TRDGRA0
in the TRD1 register
(transfer from the
buffer register to the general
register at the underflow in
the TRD1 register)
(transfer from the
buffer register to the general
register at the compare match w ith
registers TRD0 and TRDGRA0.)
After Reset
10000000b
Function
(3)
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW