R5F21257SNFP#U0 Renesas Electronics America, R5F21257SNFP#U0 Datasheet - Page 288

• Manufacturer Part Number: R5F21257SNFP#U0
• Description: IC R8C/25 MCU FLASH 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21257SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Figure 14.112 Operation when Value in Buffer Register Is Set to 0000h in Complementary PWM
14.3.12.8 Count Source fOCO40M
• The count source fOCO40M can be used with supply voltage VCC = 3.0 to 5.5 V. For supply voltage other
Feb 29, 2008
When the value in the buffer register is set to 0000h:
Transfer takes place at compare match between registers TRD0 and TRDGRA0.
After this, when the buffer register is set to 0001h or above and a smaller value than the value of the
TRDGRA0 register, and a compare match occurs between registers TRD0 and TRDGRA0 for the first time
after setting, the value is transferred to the general register. After that, the value is transferred with the
timing selected by bits CMD1 to CMD0.
than that, do not set bits TCK2 to TCK0 in registers TRDCR0 and TRDCR to 110b (select fOCO40M as
the count source).
TRDGRD0 register
TRDGRB0 register
TRDIOB0 output
TRDIOD0 output
The above applies under the following conditions:
• Bits CMD1 to CMD0 in the TRDFCR register are set to 10b (data in the buffer register is transferred at underflow of the TRD1 register in
• Both the OLS0 and OLS1 bits in the TRDFCR register are set to 1 (active “H” for normal-phase and counter-phase).
PWM mode).
Mode
0000h
m+1
n2
n1
Page 269 of 485
Transfer with timing
set by bits CMD1 to
CMD0
n2
Transfer
n1
n1
Transfer
0000h
Transfer at compare
match between
registers TRD0 and
TRDGRA0 because
content in
TRDGRD0 register
is set to 0000h
0000h
m: Value set in TRDGRA0 register
Transfer at compare
match between
registers TRD0 and
TRDGRA0 because
of first setting to
0001h ≤ n1 < m
n1
Transfer
n1
Count value in TRD0 register
Transfer with timing
set by bits CMD1 to
CMD0
Transfer
Count value in TRD1 register
14. Timers