R5F21257SNFP#U0 Renesas Electronics America, R5F21257SNFP#U0 Datasheet - Page 383

• Manufacturer Part Number: R5F21257SNFP#U0
• Description: IC R8C/25 MCU FLASH 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21257SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Figure 16.47
NOTES:
1. Do not generate the interrupt while processing steps (1) to (3).
2. When receiving 1 byte, skip steps (2) to (6) after (1) and jump to process of step (7).
Processing step (8) is dummy read of the ICDRR register.
Feb 29, 2008
ICSR register
ICCR1 register
ICSR register
ICIER register
ICIER register
ICCR1 register
ICSR register
ICCR2 register
ICCR1 register
ICCR1 register
Read RDRF bit in ICSR register
Read RDRF bit in ICSR register
Read STOP bit in ICSR register
Dummy read in ICDRR register
Example of Register Setting in Master Receive Mode (I
No
No
No
Read ICDRR register
Read ICDRR register
Read ICDRR register
Master receive mode
RDRF = 1 ?
Yes
RDRF = 1 ?
Yes
Yes
Last receive
STOP = 1 ?
ACKBT bit ← 0
ACKBT bit ← 1
TEND bit ← 0
TDRE bit ← 0
- 1 ?
RCVD bit ← 1
Page 364 of 485
STOP bit ← 0
RCVD bit ← 0
End
BBSY bit ← 0
TRS bit ← 0
SCP bit ← 0
MST bit ← 0
No
Yes
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(1) Set the TEND bit to 0 and set to master receive mode.
(2) Set the ACKBT bit to the transmit device
(3) Dummy read the ICDRR register
(4) Wait for 1 byte to be received
(5) Judge (last receive - 1)
(6) Read the receive data
(7) Set the ACKBT bit of the last byte and set to disable
(8) Read the receive data of (last byte - 1)
(9) Wait until the last byte is received
(10) Set the STOP bit to 0
(11) Generate the stop condition
(12) Wait until the stop condition is generated
(13) Read the receive data of the last byte
(14) Set the RCVD bit to 0
(15) Set to slave receive mode
Set the TDRE bit to 0
continuous receive operation (RCVD = 1)
16. Clock Synchronous Serial Interface
2
C bus Interface Mode)
(1,2)
(1)
(1)
(2)